convert addr match into latched (SRLatch) version, activate on req_rel,

[soc.git] / src / experiment / alu_hier.py

diff --git a/src/experiment/alu_hier.py b/src/experiment/alu_hier.py
index 9c753005f70b10d6c56ac2f8cdb2e35926276cae..8e3677a523c8a4ff8aa7b890d048be89ba112208 100644 (file)
--- a/src/experiment/alu_hier.py
+++ b/src/experiment/alu_hier.py
@@ -102,10 +102,10 @@ class ALU(Elaboratable):
                     m.d.sync += self.counter.eq(5)
                 with m.Elif(self.op == 3): # SHIFT to take 7
                     m.d.sync += self.counter.eq(7)
-                with m.Elif(self.op == 1): # SUB to take 2
-                    m.d.sync += self.counter.eq(2)
-                with m.Else(): # ADD to take 1, straight away
+                with m.Elif(self.op == 1): # SUB to take 1, straight away
                     m.d.sync += self.counter.eq(1)
+                with m.Else(): # ADD to take 2
+                    m.d.sync += self.counter.eq(2)
                     m.d.comb += go_now.eq(1)
         with m.Else():
             # input says no longer valid, so drop ready as well.