use opcode-base issue units, parallel units

[soc.git] / src / experiment / compalu.py

diff --git a/src/experiment/compalu.py b/src/experiment/compalu.py
index ba377b80a7d400e45b3c67c06adb0860ea898534..446c7e0f997a38295b14cd87f264645edea0673e 100644 (file)
--- a/src/experiment/compalu.py
+++ b/src/experiment/compalu.py
@@ -105,7 +105,7 @@ class ComputationUnitNoDelay(Elaboratable):
                 m.d.sync += self.counter.eq(5)
             with m.Elif(self.oper_i == 3): # SHIFT to take 7
                 m.d.sync += self.counter.eq(7)
-            with m.Elif(counter >= 4): # Branches to take 6 (to test shadow)
+            with m.Elif(self.oper_i >= 4): # Branches take 6 (to test shadow)
                 m.d.sync += self.counter.eq(6)
             with m.Else(): # ADD/SUB to take 2
                 m.d.sync += self.counter.eq(2)
@@ -122,7 +122,7 @@ class ComputationUnitNoDelay(Elaboratable):
         #    m.d.comb += self.alu.op.eq(self.oper_i)
 
         # create a latch/register for the operand
-        latchregister(m, self.oper_i, self.alu.op, src_l.q)
+        latchregister(m, self.oper_i, self.alu.op, opc_l.qn)
 
         # and one for the output from the ALU
         data_r = Signal(self.rwid, reset_less=True) # Dest register