self.rwid = rwid
self.alu = alu
+ self.counter = Signal(3)
self.go_rd_i = Signal(reset_less=True) # go read in
self.go_wr_i = Signal(reset_less=True) # go write in
self.issue_i = Signal(reset_less=True) # fn issue in
# outputs
m.d.comb += self.busy_o.eq(opc_l.q) # busy out
- m.d.comb += self.req_rel_o.eq(req_l.q & opc_l.q) # request release out
+
+ with m.If(req_l.qn & opc_l.q & (self.counter == 0)):
+ m.d.sync += self.counter.eq(5)
+ with m.If(self.counter > 0):
+ m.d.sync += self.counter.eq(self.counter - 1)
+ with m.If((self.counter == 1) | (self.counter == 0)):
+ m.d.comb += self.req_rel_o.eq(req_l.q & opc_l.q) # req release out
# create a latch/register for src1/src2
latchregister(m, self.src1_i, self.alu.a, src_l.q)