from scoreboard.fu_reg_matrix import FURegDepMatrix
from scoreboard.global_pending import GlobalPending
from scoreboard.group_picker import GroupPicker
-from scoreboard.issue_unit import IntFPIssueUnit
+from scoreboard.issue_unit import IntFPIssueUnit, RegDecode
from compalu import ComputationUnitNoDelay
from alu_hier import ALU
from nmutil.latch import SRLatch
+from random import randint
+
class Scoreboard(Elaboratable):
def __init__(self, rwid, n_regs):
m.d.comb += comp2.oper_i.eq(Const(1)) # temporary/experiment: op=sub
# Int FUs
- il = []
+ if_l = []
+ int_src1_pend_v = []
+ int_src2_pend_v = []
int_rd_pend_v = []
int_wr_pend_v = []
for i, a in enumerate(int_alus):
# set up Integer Function Unit, add to module (and python list)
fu = IntFnUnit(self.n_regs, shadow_wid=0)
setattr(m.submodules, "intfu%d" % i, fu)
- il.append(fu)
+ if_l.append(fu)
# collate the read/write pending vectors (to go into global pending)
+ int_src1_pend_v.append(fu.src1_pend_o)
+ int_src2_pend_v.append(fu.src2_pend_o)
int_rd_pend_v.append(fu.int_rd_pend_o)
int_wr_pend_v.append(fu.int_wr_pend_o)
- int_fus = Array(il)
+ int_fus = Array(if_l)
# Count of number of FUs
- n_int_fus = len(il)
+ n_int_fus = len(if_l)
n_fp_fus = 0 # for now
n_fus = n_int_fus + n_fp_fus # plus FP FUs
# Global Pending Vectors (INT and FP)
# NOTE: number of vectors is NOT same as number of FUs.
- g_int_rd_pend_v = GlobalPending(self.n_regs, int_rd_pend_v)
- g_int_wr_pend_v = GlobalPending(self.n_regs, int_wr_pend_v)
+ g_int_src1_pend_v = GlobalPending(self.n_regs, int_src1_pend_v)
+ g_int_src2_pend_v = GlobalPending(self.n_regs, int_src2_pend_v)
+ g_int_rd_pend_v = GlobalPending(self.n_regs, int_rd_pend_v, True)
+ g_int_wr_pend_v = GlobalPending(self.n_regs, int_wr_pend_v, True)
+ m.submodules.g_int_src1_pend_v = g_int_src1_pend_v
+ m.submodules.g_int_src2_pend_v = g_int_src2_pend_v
m.submodules.g_int_rd_pend_v = g_int_rd_pend_v
m.submodules.g_int_wr_pend_v = g_int_wr_pend_v
# INT/FP Issue Unit
+ regdecode = RegDecode(self.n_regs)
+ m.submodules.regdecode = regdecode
issueunit = IntFPIssueUnit(self.n_regs, n_int_fus, n_fp_fus)
m.submodules.issueunit = issueunit
+ # FU-FU Dependency Matrices
+ intfudeps = FUFUDepMatrix(n_int_fus, n_int_fus)
+ m.submodules.intfudeps = intfudeps
+
#---------
# ok start wiring things together...
# "now hear de word of de looord... dem bones dem bones dem dryy bones"
# Issue Unit is where it starts. set up some in/outs for this module
#---------
m.d.comb += [issueunit.i.store_i.eq(self.int_store_i),
- issueunit.i.dest_i.eq(self.int_dest_i),
- issueunit.i.src1_i.eq(self.int_src1_i),
- issueunit.i.src2_i.eq(self.int_src2_i),
- self.issue_o.eq(issueunit.issue_o)
+ regdecode.dest_i.eq(self.int_dest_i),
+ regdecode.src1_i.eq(self.int_src1_i),
+ regdecode.src2_i.eq(self.int_src2_i),
+ regdecode.enable_i.eq(1),
+ self.issue_o.eq(issueunit.issue_o),
+ issueunit.i.dest_i.eq(regdecode.dest_o),
]
self.int_insn_i = issueunit.i.insn_i # enabled by instruction decode
# and int function issue / busy arrays, and dest/src1/src2
fn_issue_l = []
fn_busy_l = []
- for i, fu in enumerate(il):
+ for i, fu in enumerate(if_l):
fn_issue_l.append(fu.issue_i)
fn_busy_l.append(fu.busy_o)
- # XXX sync, so as to stop a simulation infinite loop
m.d.sync += fu.issue_i.eq(issueunit.i.fn_issue_o[i])
- m.d.sync += fu.dest_i.eq(issueunit.i.dest_i)
- m.d.sync += fu.src1_i.eq(issueunit.i.src1_i)
- m.d.sync += fu.src2_i.eq(issueunit.i.src2_i)
- m.d.sync += issueunit.i.busy_i[i].eq(fu.busy_o)
+ m.d.sync += fu.dest_i.eq(self.int_dest_i)
+ m.d.sync += fu.src1_i.eq(self.int_src1_i)
+ m.d.sync += fu.src2_i.eq(self.int_src2_i)
+ # XXX sync, so as to stop a simulation infinite loop
+ m.d.comb += issueunit.i.busy_i[i].eq(fu.busy_o)
#---------
# connect Function Units
#---------
# Group Picker... done manually for now. TODO: cat array of pick sigs
- m.d.comb += il[0].go_rd_i.eq(intpick1.go_rd_o[0]) # add rd
- m.d.comb += il[0].go_wr_i.eq(intpick1.go_wr_o[0]) # add wr
+ m.d.comb += if_l[0].go_rd_i.eq(intpick1.go_rd_o[0]) # add rd
+ m.d.comb += if_l[0].go_wr_i.eq(intpick1.go_wr_o[0]) # add wr
+
+ m.d.comb += if_l[1].go_rd_i.eq(intpick1.go_rd_o[1]) # subtract rd
+ m.d.comb += if_l[1].go_wr_i.eq(intpick1.go_wr_o[1]) # subtract wr
- m.d.comb += il[1].go_rd_i.eq(intpick1.go_rd_o[1]) # subtract rd
- m.d.comb += il[1].go_wr_i.eq(intpick1.go_wr_o[1]) # subtract wr
+ # create read-pending FU-FU vectors
+ intfu_rd_pend_v = Signal(n_int_fus, reset_less = True)
+ intfu_wr_pend_v = Signal(n_int_fus, reset_less = True)
+ for i in range(n_int_fus):
+ #m.d.comb += intfu_rd_pend_v[i].eq(if_l[i].int_rd_pend_o.bool())
+ #m.d.comb += intfu_wr_pend_v[i].eq(if_l[i].int_wr_pend_o.bool())
+ m.d.comb += intfu_rd_pend_v[i].eq(if_l[i].int_readable_o)
+ m.d.comb += intfu_wr_pend_v[i].eq(if_l[i].int_writable_o)
# Connect INT Fn Unit global wr/rd pending
- for fu in il:
+ for fu in if_l:
m.d.comb += fu.g_int_wr_pend_i.eq(g_int_wr_pend_v.g_pend_o)
m.d.comb += fu.g_int_rd_pend_i.eq(g_int_rd_pend_v.g_pend_o)
- # Connect Picker
+ # Connect FU-FU Matrix, NOTE: FN Units readable/writable considered
+ # to be unit "read-pending / write-pending"
+ m.d.comb += intfudeps.rd_pend_i.eq(intfu_rd_pend_v)
+ m.d.comb += intfudeps.wr_pend_i.eq(intfu_wr_pend_v)
+ m.d.comb += intfudeps.issue_i.eq(issueunit.i.fn_issue_o)
+ for i in range(n_int_fus):
+ m.d.comb += intfudeps.go_rd_i[i].eq(intpick1.go_rd_o[i])
+ m.d.comb += intfudeps.go_wr_i[i].eq(intpick1.go_wr_o[i])
+
+ # Connect Picker (note connection to FU-FU)
#---------
+ readable_o = intfudeps.readable_o
+ writable_o = intfudeps.writable_o
+ m.d.comb += intpick1.rd_rel_i[0].eq(int_alus[0].rd_rel_o)
+ m.d.comb += intpick1.rd_rel_i[1].eq(int_alus[1].rd_rel_o)
m.d.comb += intpick1.req_rel_i[0].eq(int_alus[0].req_rel_o)
m.d.comb += intpick1.req_rel_i[1].eq(int_alus[1].req_rel_o)
- m.d.comb += intpick1.readable_i[0].eq(il[0].int_readable_o) # add rdable
- m.d.comb += intpick1.writable_i[0].eq(il[0].int_writable_o) # add rdable
- m.d.comb += intpick1.readable_i[1].eq(il[1].int_readable_o) # sub rdable
- m.d.comb += intpick1.writable_i[1].eq(il[1].int_writable_o) # sub rdable
+ m.d.comb += intpick1.readable_i[0].eq(readable_o[0]) # add rd
+ m.d.comb += intpick1.writable_i[0].eq(writable_o[0]) # add wr
+ m.d.comb += intpick1.readable_i[1].eq(readable_o[1]) # sub rd
+ m.d.comb += intpick1.writable_i[1].eq(writable_o[1]) # sub wr
#---------
# Connect Register File(s)
#---------
- m.d.comb += int_dest.wen.eq(g_int_wr_pend_v.g_pend_o)
- m.d.comb += int_src1.ren.eq(g_int_rd_pend_v.g_pend_o)
- m.d.comb += int_src2.ren.eq(g_int_rd_pend_v.g_pend_o)
+ #with m.If(if_l[0].go_wr_i | if_l[1].go_wr_i):
+ m.d.sync += int_dest.wen.eq(g_int_wr_pend_v.g_pend_o)
+ #with m.If(intpick1.go_rd_o):
+ #with m.If(if_l[0].go_rd_i | if_l[1].go_rd_i):
+ m.d.sync += int_src1.ren.eq(g_int_src1_pend_v.g_pend_o)
+ m.d.sync += int_src2.ren.eq(g_int_src2_pend_v.g_pend_o)
# merge (OR) all integer FU / ALU outputs to a single value
# bit of a hack: treereduce needs a list with an item named "dest_o"
dest_o = treereduce(int_alus)
- m.d.comb += int_dest.data_i.eq(dest_o)
+ m.d.sync += int_dest.data_i.eq(dest_o)
# connect ALUs
for i, alu in enumerate(int_alus):
- m.d.comb += alu.go_rd_i.eq(il[i].go_rd_i) # chained from intpick
- m.d.comb += alu.go_wr_i.eq(il[i].go_wr_i) # chained from intpick
+ m.d.comb += alu.go_rd_i.eq(intpick1.go_rd_o[i])
+ m.d.comb += alu.go_wr_i.eq(intpick1.go_wr_o[i])
m.d.comb += alu.issue_i.eq(fn_issue_l[i])
#m.d.comb += fn_busy_l[i].eq(alu.busy_o) # XXX ignore, use fnissue
m.d.comb += alu.src1_i.eq(int_src1.data_o)
m.d.comb += alu.src2_i.eq(int_src2.data_o)
- m.d.comb += il[i].req_rel_i.eq(alu.req_rel_o) # pipe out ready
+ m.d.comb += if_l[i].req_rel_i.eq(alu.req_rel_o) # pipe out ready
return m
IADD = 0
ISUB = 1
-def int_instr(dut, op, src1, src2, dest):
+class RegSim:
+ def __init__(self, rwidth, nregs):
+ self.rwidth = rwidth
+ self.regs = [0] * nregs
+
+ def op(self, op, src1, src2, dest):
+ src1 = self.regs[src1]
+ src2 = self.regs[src2]
+ if op == IADD:
+ val = (src1 + src2) & ((1<<(self.rwidth))-1)
+ elif op == ISUB:
+ val = (src1 - src2) & ((1<<(self.rwidth))-1)
+ self.regs[dest] = val
+
+ def setval(self, dest, val):
+ self.regs[dest] = val
+
+ def dump(self, dut):
+ for i, val in enumerate(self.regs):
+ reg = yield dut.intregs.regs[i].reg
+ okstr = "OK" if reg == val else "!ok"
+ print("reg %d expected %x received %x %s" % (i, val, reg, okstr))
+
+ def check(self, dut):
+ for i, val in enumerate(self.regs):
+ reg = yield dut.intregs.regs[i].reg
+ if reg != val:
+ print("reg %d expected %x received %x\n" % (i, val, reg))
+ yield from self.dump(dut)
+ assert False
+
+def int_instr(dut, alusim, op, src1, src2, dest):
+ for i in range(len(dut.int_insn_i)):
+ yield dut.int_insn_i[i].eq(0)
yield dut.int_dest_i.eq(dest)
yield dut.int_src1_i.eq(src1)
yield dut.int_src2_i.eq(src2)
yield dut.int_insn_i[op].eq(1)
+ alusim.op(op, src1, src2, dest)
-def print_reg(dut, rnum):
- reg = yield dut.intregs.regs[5].reg
- print ("reg %d: %x" % (rnum, reg))
-def scoreboard_sim(dut):
+def print_reg(dut, rnums):
+ rs = []
+ for rnum in rnums:
+ reg = yield dut.intregs.regs[rnum].reg
+ rs.append("%x" % reg)
+ rnums = map(str, rnums)
+ print ("reg %s: %s" % (','.join(rnums), ','.join(rs)))
+
+
+def scoreboard_sim(dut, alusim):
+ yield dut.int_store_i.eq(0)
+
for i in range(1, dut.n_regs):
yield dut.intregs.regs[i].reg.eq(i)
+ alusim.setval(i, i)
+
+ if False:
+ yield from int_instr(dut, alusim, IADD, 4, 3, 5)
+ yield from print_reg(dut, [3,4,5])
+ yield
+ yield from int_instr(dut, alusim, IADD, 5, 2, 5)
+ yield from print_reg(dut, [3,4,5])
+ yield
+ yield from int_instr(dut, alusim, ISUB, 5, 1, 3)
+ yield from print_reg(dut, [3,4,5])
+ yield
+ for i in range(len(dut.int_insn_i)):
+ yield dut.int_insn_i[i].eq(0)
+ yield from print_reg(dut, [3,4,5])
+ yield
+ yield from print_reg(dut, [3,4,5])
+ yield
+ yield from print_reg(dut, [3,4,5])
+ yield
+
+ yield from alusim.check(dut)
+
+ for i in range(2):
+ src1 = randint(1, dut.n_regs-1)
+ src2 = randint(1, dut.n_regs-1)
+ while True:
+ dest = randint(1, dut.n_regs-1)
+ break
+ if dest not in [src1, src2]:
+ break
+ op = randint(0, 1)
+ if False:
+ if i % 2 == 0:
+ src1 = 6
+ src2 = 6
+ dest = 1
+ else:
+ src1 = 1
+ src2 = 7
+ dest = 2
+ #src1 = 2
+ #src2 = 3
+ #dest = 2
+
+ op = i
+
+ if True:
+ if i == 0:
+ src1 = 2
+ src2 = 3
+ dest = 3
+ else:
+ src1 = 5
+ src2 = 3
+ dest = 4
+
+ #op = (i+1) % 2
+ op = i
+
+ print ("random %d: %d %d %d %d\n" % (i, op, src1, src2, dest))
+ yield from int_instr(dut, alusim, op, src1, src2, dest)
+ yield from print_reg(dut, [3,4,5])
+ while True:
+ yield
+ issue_o = yield dut.issue_o
+ if issue_o:
+ yield from print_reg(dut, [3,4,5])
+ for i in range(len(dut.int_insn_i)):
+ yield dut.int_insn_i[i].eq(0)
+ break
+ print ("busy",)
+ yield from print_reg(dut, [3,4,5])
+ yield
+ yield
+ yield
+
+
+ yield
+ yield from print_reg(dut, [3,4,5])
yield
- yield from int_instr(dut, IADD, 4, 1, 5)
- yield from print_reg(dut, 5)
+ yield from print_reg(dut, [3,4,5])
yield
- yield from print_reg(dut, 5)
+ yield from print_reg(dut, [3,4,5])
yield
- yield from print_reg(dut, 5)
+ yield from print_reg(dut, [3,4,5])
yield
- yield from print_reg(dut, 5)
yield
- yield from print_reg(dut, 5)
yield
+ yield
+ yield
+ yield
+ yield
+ yield
+ yield
+ yield from alusim.check(dut)
+ yield from alusim.dump(dut)
+
+
+def explore_groups(dut):
+ from nmigen.hdl.ir import Fragment
+ from nmigen.hdl.xfrm import LHSGroupAnalyzer
+
+ fragment = dut.elaborate(platform=None)
+ fr = Fragment.get(fragment, platform=None)
+
+ groups = LHSGroupAnalyzer()(fragment._statements)
+
+ print (groups)
def test_scoreboard():
- dut = Scoreboard(32, 8)
+ dut = Scoreboard(16, 8)
+ alusim = RegSim(16, 8)
vl = rtlil.convert(dut, ports=dut.ports())
with open("test_scoreboard.il", "w") as f:
f.write(vl)
- run_simulation(dut, scoreboard_sim(dut), vcd_name='test_scoreboard.vcd')
+ run_simulation(dut, scoreboard_sim(dut, alusim),
+ vcd_name='test_scoreboard.vcd')
if __name__ == '__main__':
projects / soc.git / blobdiff