issueunit = IntFPIssueUnit(self.n_regs, n_int_fus, n_fp_fus)
m.submodules.issueunit = issueunit
+ # FU-FU Dependency Matrices
+ intfudeps = FUFUDepMatrix(n_int_fus, n_int_fus)
+ m.submodules.intfudeps = intfudeps
+
#---------
# ok start wiring things together...
# "now hear de word of de looord... dem bones dem bones dem dryy bones"
regdecode.src1_i.eq(self.int_src1_i),
regdecode.src2_i.eq(self.int_src2_i),
regdecode.enable_i.eq(1),
- self.issue_o.eq(issueunit.issue_o)
+ self.issue_o.eq(issueunit.issue_o),
+ issueunit.i.dest_i.eq(regdecode.dest_o),
]
- m.d.sync += issueunit.i.dest_i.eq(regdecode.dest_o),
self.int_insn_i = issueunit.i.insn_i # enabled by instruction decode
# connect global rd/wr pending vectors
# connect Function Units
#---------
- # XXX sync, again to avoid an infinite loop. is it the right thing???
-
# Group Picker... done manually for now. TODO: cat array of pick sigs
- m.d.sync += if_l[0].go_rd_i.eq(intpick1.go_rd_o[0]) # add rd
- m.d.sync += if_l[0].go_wr_i.eq(intpick1.go_wr_o[0]) # add wr
+ m.d.comb += if_l[0].go_rd_i.eq(intpick1.go_rd_o[0]) # add rd
+ m.d.comb += if_l[0].go_wr_i.eq(intpick1.go_wr_o[0]) # add wr
- m.d.sync += if_l[1].go_rd_i.eq(intpick1.go_rd_o[1]) # subtract rd
- m.d.sync += if_l[1].go_wr_i.eq(intpick1.go_wr_o[1]) # subtract wr
+ m.d.comb += if_l[1].go_rd_i.eq(intpick1.go_rd_o[1]) # subtract rd
+ m.d.comb += if_l[1].go_wr_i.eq(intpick1.go_wr_o[1]) # subtract wr
+
+ # create read-pending FU-FU vectors
+ intfu_rd_pend_v = Signal(n_int_fus, reset_less = True)
+ intfu_wr_pend_v = Signal(n_int_fus, reset_less = True)
+ for i in range(n_int_fus):
+ #m.d.comb += intfu_rd_pend_v[i].eq(if_l[i].int_rd_pend_o.bool())
+ #m.d.comb += intfu_wr_pend_v[i].eq(if_l[i].int_wr_pend_o.bool())
+ m.d.comb += intfu_rd_pend_v[i].eq(if_l[i].int_readable_o)
+ m.d.comb += intfu_wr_pend_v[i].eq(if_l[i].int_writable_o)
# Connect INT Fn Unit global wr/rd pending
for fu in if_l:
m.d.comb += fu.g_int_wr_pend_i.eq(g_int_wr_pend_v.g_pend_o)
m.d.comb += fu.g_int_rd_pend_i.eq(g_int_rd_pend_v.g_pend_o)
- # Connect Picker
+ # Connect FU-FU Matrix, NOTE: FN Units readable/writable considered
+ # to be unit "read-pending / write-pending"
+ m.d.comb += intfudeps.rd_pend_i.eq(intfu_rd_pend_v)
+ m.d.comb += intfudeps.wr_pend_i.eq(intfu_wr_pend_v)
+ m.d.comb += intfudeps.issue_i.eq(issueunit.i.fn_issue_o)
+ for i in range(n_int_fus):
+ m.d.comb += intfudeps.go_rd_i[i].eq(intpick1.go_rd_o[i])
+ m.d.comb += intfudeps.go_wr_i[i].eq(intpick1.go_wr_o[i])
+
+ # Connect Picker (note connection to FU-FU)
#---------
- m.d.comb += intpick1.go_rd_i[0].eq(~if_l[0].go_rd_i)
- m.d.comb += intpick1.go_rd_i[1].eq(~if_l[1].go_rd_i)
+ readable_o = intfudeps.readable_o
+ writable_o = intfudeps.writable_o
+ m.d.comb += intpick1.rd_rel_i[0].eq(int_alus[0].rd_rel_o)
+ m.d.comb += intpick1.rd_rel_i[1].eq(int_alus[1].rd_rel_o)
m.d.comb += intpick1.req_rel_i[0].eq(int_alus[0].req_rel_o)
m.d.comb += intpick1.req_rel_i[1].eq(int_alus[1].req_rel_o)
- m.d.comb += intpick1.readable_i[0].eq(if_l[0].int_readable_o) # add rd
- m.d.comb += intpick1.writable_i[0].eq(if_l[0].int_writable_o) # add wr
- m.d.comb += intpick1.readable_i[1].eq(if_l[1].int_readable_o) # sub rd
- m.d.comb += intpick1.writable_i[1].eq(if_l[1].int_writable_o) # sub wr
+ m.d.comb += intpick1.readable_i[0].eq(readable_o[0]) # add rd
+ m.d.comb += intpick1.writable_i[0].eq(writable_o[0]) # add wr
+ m.d.comb += intpick1.readable_i[1].eq(readable_o[1]) # sub rd
+ m.d.comb += intpick1.writable_i[1].eq(writable_o[1]) # sub wr
#---------
# Connect Register File(s)
#---------
- with m.If(if_l[0].go_wr_i | if_l[1].go_wr_i):
- m.d.comb += int_dest.wen.eq(g_int_wr_pend_v.g_pend_o)
+ #with m.If(if_l[0].go_wr_i | if_l[1].go_wr_i):
+ m.d.sync += int_dest.wen.eq(g_int_wr_pend_v.g_pend_o)
#with m.If(intpick1.go_rd_o):
#with m.If(if_l[0].go_rd_i | if_l[1].go_rd_i):
- m.d.comb += int_src1.ren.eq(g_int_src1_pend_v.g_pend_o)
- m.d.comb += int_src2.ren.eq(g_int_src2_pend_v.g_pend_o)
+ m.d.sync += int_src1.ren.eq(g_int_src1_pend_v.g_pend_o)
+ m.d.sync += int_src2.ren.eq(g_int_src2_pend_v.g_pend_o)
# merge (OR) all integer FU / ALU outputs to a single value
# bit of a hack: treereduce needs a list with an item named "dest_o"
dest_o = treereduce(int_alus)
- m.d.comb += int_dest.data_i.eq(dest_o)
+ m.d.sync += int_dest.data_i.eq(dest_o)
# connect ALUs
for i, alu in enumerate(int_alus):
- m.d.sync += alu.go_rd_i.eq(intpick1.go_rd_o[i])
- m.d.sync += alu.go_wr_i.eq(intpick1.go_wr_o[i])
+ m.d.comb += alu.go_rd_i.eq(intpick1.go_rd_o[i])
+ m.d.comb += alu.go_wr_i.eq(intpick1.go_wr_o[i])
m.d.comb += alu.issue_i.eq(fn_issue_l[i])
#m.d.comb += fn_busy_l[i].eq(alu.busy_o) # XXX ignore, use fnissue
m.d.comb += alu.src1_i.eq(int_src1.data_o)
break
print ("busy",)
yield from print_reg(dut, [3,4,5])
+ yield
+ yield
+ yield
yield
projects / soc.git / blobdiff