# NOTE: number of vectors is NOT same as number of FUs.
g_int_src1_pend_v = GlobalPending(self.n_regs, int_src1_pend_v)
g_int_src2_pend_v = GlobalPending(self.n_regs, int_src2_pend_v)
- g_int_rd_pend_v = GlobalPending(self.n_regs, int_rd_pend_v)
- g_int_wr_pend_v = GlobalPending(self.n_regs, int_wr_pend_v)
+ g_int_rd_pend_v = GlobalPending(self.n_regs, int_rd_pend_v, True)
+ g_int_wr_pend_v = GlobalPending(self.n_regs, int_wr_pend_v, True)
m.submodules.g_int_src1_pend_v = g_int_src1_pend_v
m.submodules.g_int_src2_pend_v = g_int_src2_pend_v
m.submodules.g_int_rd_pend_v = g_int_rd_pend_v
issueunit = IntFPIssueUnit(self.n_regs, n_int_fus, n_fp_fus)
m.submodules.issueunit = issueunit
+ # FU-FU Dependency Matrices
+ intfudeps = FUFUDepMatrix(n_int_fus, n_int_fus)
+ m.submodules.intfudeps = intfudeps
+
#---------
# ok start wiring things together...
# "now hear de word of de looord... dem bones dem bones dem dryy bones"
regdecode.src1_i.eq(self.int_src1_i),
regdecode.src2_i.eq(self.int_src2_i),
regdecode.enable_i.eq(1),
- issueunit.i.dest_i.eq(regdecode.dest_o),
- self.issue_o.eq(issueunit.issue_o)
+ self.issue_o.eq(issueunit.issue_o),
+ issueunit.i.dest_i.eq(regdecode.dest_o),
]
self.int_insn_i = issueunit.i.insn_i # enabled by instruction decode
fn_issue_l.append(fu.issue_i)
fn_busy_l.append(fu.busy_o)
m.d.sync += fu.issue_i.eq(issueunit.i.fn_issue_o[i])
- m.d.comb += fu.dest_i.eq(self.int_dest_i)
- m.d.comb += fu.src1_i.eq(self.int_src1_i)
- m.d.comb += fu.src2_i.eq(self.int_src2_i)
+ m.d.sync += fu.dest_i.eq(self.int_dest_i)
+ m.d.sync += fu.src1_i.eq(self.int_src1_i)
+ m.d.sync += fu.src2_i.eq(self.int_src2_i)
# XXX sync, so as to stop a simulation infinite loop
m.d.comb += issueunit.i.busy_i[i].eq(fu.busy_o)
m.d.sync += if_l[1].go_rd_i.eq(intpick1.go_rd_o[1]) # subtract rd
m.d.sync += if_l[1].go_wr_i.eq(intpick1.go_wr_o[1]) # subtract wr
+ # create read-pending FU-FU vectors
+ intfu_rd_pend_v = Signal(n_int_fus, reset_less = True)
+ intfu_wr_pend_v = Signal(n_int_fus, reset_less = True)
+ for i in range(n_int_fus):
+ #m.d.comb += intfu_rd_pend_v[i].eq(if_l[i].int_rd_pend_o.bool())
+ #m.d.comb += intfu_wr_pend_v[i].eq(if_l[i].int_wr_pend_o.bool())
+ m.d.comb += intfu_rd_pend_v[i].eq(if_l[i].int_readable_o)
+ m.d.comb += intfu_wr_pend_v[i].eq(if_l[i].int_writable_o)
+
# Connect INT Fn Unit global wr/rd pending
for fu in if_l:
- m.d.sync += fu.g_int_wr_pend_i.eq(g_int_wr_pend_v.g_pend_o)
- m.d.sync += fu.g_int_rd_pend_i.eq(g_int_rd_pend_v.g_pend_o)
-
- # Connect Picker
+ m.d.comb += fu.g_int_wr_pend_i.eq(g_int_wr_pend_v.g_pend_o)
+ m.d.comb += fu.g_int_rd_pend_i.eq(g_int_rd_pend_v.g_pend_o)
+
+ # Connect FU-FU Matrix, NOTE: FN Units readable/writable considered
+ # to be unit "read-pending / write-pending"
+ m.d.comb += intfudeps.rd_pend_i.eq(intfu_rd_pend_v)
+ m.d.comb += intfudeps.wr_pend_i.eq(intfu_wr_pend_v)
+ m.d.sync += intfudeps.issue_i.eq(issueunit.i.fn_issue_o)
+ for i in range(n_int_fus):
+ m.d.sync += intfudeps.go_rd_i[i].eq(intpick1.go_rd_o[i])
+ m.d.sync += intfudeps.go_wr_i[i].eq(intpick1.go_wr_o[i])
+
+ # Connect Picker (note connection to FU-FU)
#---------
+ readable_o = intfudeps.readable_o
+ writable_o = intfudeps.writable_o
+ m.d.comb += intpick1.go_rd_i[0].eq(~if_l[0].go_rd_i)
+ m.d.comb += intpick1.go_rd_i[1].eq(~if_l[1].go_rd_i)
m.d.comb += intpick1.req_rel_i[0].eq(int_alus[0].req_rel_o)
m.d.comb += intpick1.req_rel_i[1].eq(int_alus[1].req_rel_o)
- m.d.comb += intpick1.readable_i[0].eq(if_l[0].int_readable_o) # add rd
- m.d.comb += intpick1.writable_i[0].eq(if_l[0].int_writable_o) # add wr
- m.d.comb += intpick1.readable_i[1].eq(if_l[1].int_readable_o) # sub rd
- m.d.comb += intpick1.writable_i[1].eq(if_l[1].int_writable_o) # sub wr
+ m.d.comb += intpick1.readable_i[0].eq(readable_o[0]) # add rd
+ m.d.comb += intpick1.writable_i[0].eq(writable_o[0]) # add wr
+ m.d.comb += intpick1.readable_i[1].eq(readable_o[1]) # sub rd
+ m.d.comb += intpick1.writable_i[1].eq(writable_o[1]) # sub wr
#---------
# Connect Register File(s)
#---------
- m.d.sync += int_dest.wen.eq(g_int_wr_pend_v.g_pend_o)
+ with m.If(if_l[0].go_wr_i | if_l[1].go_wr_i):
+ m.d.comb += int_dest.wen.eq(g_int_wr_pend_v.g_pend_o)
+ #with m.If(intpick1.go_rd_o):
+ #with m.If(if_l[0].go_rd_i | if_l[1].go_rd_i):
m.d.comb += int_src1.ren.eq(g_int_src1_pend_v.g_pend_o)
m.d.comb += int_src2.ren.eq(g_int_src2_pend_v.g_pend_o)
break
if dest not in [src1, src2]:
break
- if i == 0:
- src1 = 6
- src2 = 6
- dest = 1
- else:
- src1 = 1
- src2 = 7
- dest = 1
- #src1 = 2
- #src2 = 3
- #dest = 2
-
op = randint(0, 1)
- op = 0
+ if False:
+ if i % 2 == 0:
+ src1 = 6
+ src2 = 6
+ dest = 1
+ else:
+ src1 = 1
+ src2 = 7
+ dest = 2
+ #src1 = 2
+ #src2 = 3
+ #dest = 2
+
+ op = i
+
+ if True:
+ if i == 0:
+ src1 = 2
+ src2 = 3
+ dest = 3
+ else:
+ src1 = 5
+ src2 = 3
+ dest = 4
+
+ #op = (i+1) % 2
+ op = i
+
print ("random %d: %d %d %d %d\n" % (i, op, src1, src2, dest))
yield from int_instr(dut, alusim, op, src1, src2, dest)
yield from print_reg(dut, [3,4,5])
- yield
- yield from print_reg(dut, [3,4,5])
- for i in range(len(dut.int_insn_i)):
- yield dut.int_insn_i[i].eq(0)
- yield
- yield
- yield
- yield
while True:
+ yield
issue_o = yield dut.issue_o
if issue_o:
+ yield from print_reg(dut, [3,4,5])
+ for i in range(len(dut.int_insn_i)):
+ yield dut.int_insn_i[i].eq(0)
break
- yield
+ print ("busy",)
+ yield from print_reg(dut, [3,4,5])
+ yield
+ yield
+ yield
+ yield
yield
yield
yield
yield
+ yield
+ yield
+ yield
yield from alusim.check(dut)
+ yield from alusim.dump(dut)
def explore_groups(dut):
def test_scoreboard():
- dut = Scoreboard(32, 8)
- alusim = RegSim(32, 8)
+ dut = Scoreboard(16, 8)
+ alusim = RegSim(16, 8)
vl = rtlil.convert(dut, ports=dut.ports())
with open("test_scoreboard.il", "w") as f:
f.write(vl)
projects / soc.git / blobdiff