from random import randint
+class CompUnits(Elaboratable):
+
+ def __init__(self, rwid, n_units):
+ """ Inputs:
+
+ * :rwid: bit width of register file(s) - both FP and INT
+ * :n_units: number of ALUs
+ """
+ self.n_units = n_units
+ self.rwid = rwid
+
+ self.issue_i = Signal(n_units, reset_less=True)
+ self.go_rd_i = Signal(n_units, reset_less=True)
+ self.go_wr_i = Signal(n_units, reset_less=True)
+ self.req_rel_o = Signal(n_units, reset_less=True)
+
+ self.dest_o = Signal(rwid, reset_less=True)
+ self.src1_data_i = Signal(rwid, reset_less=True)
+ self.src2_data_i = Signal(rwid, reset_less=True)
+
+ def elaborate(self, platform):
+ m = Module()
+
+ # Int ALUs
+ add = ALU(self.rwid)
+ sub = ALU(self.rwid)
+ m.submodules.comp1 = comp1 = ComputationUnitNoDelay(self.rwid, 1, add)
+ m.submodules.comp2 = comp2 = ComputationUnitNoDelay(self.rwid, 1, sub)
+ int_alus = [comp1, comp2]
+
+ m.d.comb += comp1.oper_i.eq(Const(0)) # temporary/experiment: op=add
+ m.d.comb += comp2.oper_i.eq(Const(1)) # temporary/experiment: op=sub
+
+ go_rd_l = []
+ go_wr_l = []
+ issue_l = []
+ req_rel_l = []
+ for alu in int_alus:
+ req_rel_l.append(alu.req_rel_o)
+ go_wr_l.append(alu.go_wr_i)
+ go_rd_l.append(alu.go_rd_i)
+ issue_l.append(alu.issue_i)
+ m.d.comb += self.req_rel_o.eq(Cat(*req_rel_l))
+ m.d.comb += Cat(*go_wr_l).eq(self.go_wr_i)
+ m.d.comb += Cat(*go_rd_l).eq(self.go_rd_i)
+ m.d.comb += Cat(*issue_l).eq(self.issue_i)
+
+ # connect data register input/output
+
+ # merge (OR) all integer FU / ALU outputs to a single value
+ # bit of a hack: treereduce needs a list with an item named "dest_o"
+ dest_o = treereduce(int_alus)
+ m.d.comb += self.dest_o.eq(dest_o)
+
+ for i, alu in enumerate(int_alus):
+ m.d.comb += alu.src1_i.eq(self.src1_data_i)
+ m.d.comb += alu.src2_i.eq(self.src2_data_i)
+
+ return m
+
+class FunctionUnits(Elaboratable):
+
+ def __init__(self, n_regs, n_int_alus):
+ self.n_regs = n_regs
+ self.n_int_alus = n_int_alus
+
+ self.int_dest_i = Signal(max=n_regs, reset_less=True) # Dest R# in
+ self.int_src1_i = Signal(max=n_regs, reset_less=True) # oper1 R# in
+ self.int_src2_i = Signal(max=n_regs, reset_less=True) # oper2 R# in
+
+ self.req_rel_i = Signal(n_int_alus, reset_less = True)
+ self.g_int_rd_pend_o = Signal(n_regs, reset_less=True)
+ self.g_int_wr_pend_o = Signal(n_regs, reset_less=True)
+
+ self.go_rd_i = Signal(n_int_alus, reset_less=True)
+ self.go_wr_i = Signal(n_int_alus, reset_less=True)
+ self.req_rel_o = Signal(n_int_alus, reset_less=True)
+ self.fn_issue_i = Signal(n_int_alus, reset_less=True)
+ self.fn_busy_o = Signal(n_int_alus, reset_less=True)
+
+ def elaborate(self, platform):
+ m = Module()
+
+ # Int FUs
+ if_l = []
+ int_src1_pend_v = []
+ int_src2_pend_v = []
+ int_rd_pend_v = []
+ int_wr_pend_v = []
+ for i in range(self.n_int_alus):
+ # set up Integer Function Unit, add to module (and python list)
+ fu = IntFnUnit(self.n_regs, shadow_wid=0)
+ setattr(m.submodules, "intfu%d" % i, fu)
+ if_l.append(fu)
+ # collate the read/write pending vectors (to go into global pending)
+ int_src1_pend_v.append(fu.src1_pend_o)
+ int_src2_pend_v.append(fu.src2_pend_o)
+ int_rd_pend_v.append(fu.int_rd_pend_o)
+ int_wr_pend_v.append(fu.int_wr_pend_o)
+ int_fus = Array(if_l)
+
+ # Global Pending Vectors (INT and TODO FP)
+ # NOTE: number of vectors is NOT same as number of FUs.
+ g_int_src1_pend_v = GlobalPending(self.n_regs, int_src1_pend_v)
+ g_int_src2_pend_v = GlobalPending(self.n_regs, int_src2_pend_v)
+ g_int_rd_pend_v = GlobalPending(self.n_regs, int_rd_pend_v)
+ g_int_wr_pend_v = GlobalPending(self.n_regs, int_wr_pend_v)
+ m.submodules.g_int_src1_pend_v = g_int_src1_pend_v
+ m.submodules.g_int_src2_pend_v = g_int_src2_pend_v
+ m.submodules.g_int_rd_pend_v = g_int_rd_pend_v
+ m.submodules.g_int_wr_pend_v = g_int_wr_pend_v
+
+ m.d.sync += self.g_int_rd_pend_o.eq(g_int_rd_pend_v.g_pend_o)
+ m.d.sync += self.g_int_wr_pend_o.eq(g_int_wr_pend_v.g_pend_o)
+
+ # Connect INT Fn Unit global wr/rd pending
+ for fu in if_l:
+ m.d.comb += fu.g_int_wr_pend_i.eq(self.g_int_wr_pend_o)
+ m.d.comb += fu.g_int_rd_pend_i.eq(self.g_int_rd_pend_o)
+
+ # Connect function issue / busy arrays, and dest/src1/src2
+ fn_busy_l = []
+ fn_issue_l = []
+ req_rel_l = []
+ go_rd_l = []
+ go_wr_l = []
+ for i, fu in enumerate(if_l):
+ fn_issue_l.append(fu.issue_i)
+ fn_busy_l.append(fu.busy_o)
+ go_wr_l.append(fu.go_wr_i)
+ go_rd_l.append(fu.go_rd_i)
+ req_rel_l.append(fu.req_rel_i)
+
+ m.d.comb += fu.dest_i.eq(self.int_dest_i)
+ m.d.comb += fu.src1_i.eq(self.int_src1_i)
+ m.d.comb += fu.src2_i.eq(self.int_src2_i)
+
+ m.d.comb += Cat(*req_rel_l).eq(self.req_rel_i)
+ m.d.comb += Cat(*fn_issue_l).eq(self.fn_issue_i)
+ m.d.comb += self.fn_busy_o.eq(Cat(*fn_busy_l))
+ m.d.comb += Cat(*go_wr_l).eq(self.go_wr_i)
+ m.d.comb += Cat(*go_rd_l).eq(self.go_rd_i)
+
+
+ return m
+
class Scoreboard(Elaboratable):
def __init__(self, rwid, n_regs):
fp_src1 = self.fpregs.read_port("src1")
fp_src2 = self.fpregs.read_port("src2")
- # Int ALUs
- add = ALU(self.rwid)
- sub = ALU(self.rwid)
- m.submodules.comp1 = comp1 = ComputationUnitNoDelay(self.rwid, 1, add)
- m.submodules.comp2 = comp2 = ComputationUnitNoDelay(self.rwid, 1, sub)
- int_alus = [comp1, comp2]
-
- m.d.comb += comp1.oper_i.eq(Const(0)) # temporary/experiment: op=add
- m.d.comb += comp2.oper_i.eq(Const(1)) # temporary/experiment: op=sub
+ # Int ALUs and Comp Units
+ n_int_alus = 2
+ m.submodules.cu = cu = CompUnits(self.rwid, n_int_alus)
# Int FUs
- if_l = []
- int_src1_pend_v = []
- int_src2_pend_v = []
- int_rd_pend_v = []
- int_wr_pend_v = []
- for i, a in enumerate(int_alus):
- # set up Integer Function Unit, add to module (and python list)
- fu = IntFnUnit(self.n_regs, shadow_wid=0)
- setattr(m.submodules, "intfu%d" % i, fu)
- if_l.append(fu)
- # collate the read/write pending vectors (to go into global pending)
- int_src1_pend_v.append(fu.src1_pend_o)
- int_src2_pend_v.append(fu.src2_pend_o)
- int_rd_pend_v.append(fu.int_rd_pend_o)
- int_wr_pend_v.append(fu.int_wr_pend_o)
- int_fus = Array(if_l)
+ m.submodules.intfus = intfus = FunctionUnits(self.n_regs, n_int_alus)
# Count of number of FUs
- n_int_fus = len(if_l)
+ n_int_fus = n_int_alus
n_fp_fus = 0 # for now
n_fus = n_int_fus + n_fp_fus # plus FP FUs
intpick1 = GroupPicker(2) # picks between add and sub
m.submodules.intpick1 = intpick1
- # Global Pending Vectors (INT and TODO FP)
- # NOTE: number of vectors is NOT same as number of FUs.
- g_int_src1_pend_v = GlobalPending(self.n_regs, int_src1_pend_v)
- g_int_src2_pend_v = GlobalPending(self.n_regs, int_src2_pend_v)
- g_int_rd_pend_v = GlobalPending(self.n_regs, int_rd_pend_v)
- g_int_wr_pend_v = GlobalPending(self.n_regs, int_wr_pend_v)
- m.submodules.g_int_src1_pend_v = g_int_src1_pend_v
- m.submodules.g_int_src2_pend_v = g_int_src2_pend_v
- m.submodules.g_int_rd_pend_v = g_int_rd_pend_v
- m.submodules.g_int_wr_pend_v = g_int_wr_pend_v
-
# INT/FP Issue Unit
regdecode = RegDecode(self.n_regs)
m.submodules.regdecode = regdecode
self.int_insn_i = issueunit.i.insn_i # enabled by instruction decode
# connect global rd/wr pending vectors
- m.d.comb += issueunit.i.g_wr_pend_i.eq(g_int_wr_pend_v.g_pend_o)
+ m.d.comb += issueunit.i.g_wr_pend_i.eq(intfus.g_int_wr_pend_o)
# TODO: issueunit.f (FP)
# and int function issue / busy arrays, and dest/src1/src2
- fn_busy_l = []
- fn_issue_l = []
- for i, fu in enumerate(if_l):
- fn_issue_l.append(fu.issue_i)
- fn_busy_l.append(fu.busy_o)
- m.d.sync += fu.issue_i.eq(issueunit.i.fn_issue_o[i])
- m.d.comb += fu.dest_i.eq(self.int_dest_i)
- m.d.comb += fu.src1_i.eq(self.int_src1_i)
- m.d.comb += fu.src2_i.eq(self.int_src2_i)
- # XXX sync, so as to stop a simulation infinite loop
- m.d.comb += issueunit.i.busy_i[i].eq(fu.busy_o)
+ m.d.comb += intfus.int_dest_i.eq(self.int_dest_i)
+ m.d.comb += intfus.int_src1_i.eq(self.int_src1_i)
+ m.d.comb += intfus.int_src2_i.eq(self.int_src2_i)
+
+ fn_issue_o = issueunit.i.fn_issue_o
+
+ m.d.comb += intfus.fn_issue_i.eq(fn_issue_o)
+ # XXX sync, so as to stop a simulation infinite loop
+ m.d.sync += issueunit.i.busy_i.eq(intfus.fn_busy_o)
- fn_issue_o = Signal(len(fn_issue_l), reset_less=True)
- m.d.comb += fn_issue_o.eq(Cat(*fn_issue_l))
- #fn_issue_o = issueunit.i.fn_issue_o
#---------
# connect fu-fu matrix
#---------
- m.d.comb += intfudeps.rd_pend_i.eq(g_int_rd_pend_v.g_pend_o)
- m.d.comb += intfudeps.wr_pend_i.eq(g_int_wr_pend_v.g_pend_o)
+ m.d.comb += intfudeps.rd_pend_i.eq(intfus.g_int_rd_pend_o)
+ m.d.comb += intfudeps.wr_pend_i.eq(intfus.g_int_wr_pend_o)
# Group Picker... done manually for now. TODO: cat array of pick sigs
+ go_rd_o = intpick1.go_rd_o
+ go_wr_o = intpick1.go_wr_o
go_rd_i = intfudeps.go_rd_i
go_wr_i = intfudeps.go_wr_i
- m.d.sync += go_rd_i[0].eq(intpick1.go_rd_o[0]) # add rd
- m.d.sync += go_wr_i[0].eq(intpick1.go_wr_o[0]) # add wr
-
- m.d.sync += go_rd_i[1].eq(intpick1.go_rd_o[1]) # sub rd
- m.d.sync += go_wr_i[1].eq(intpick1.go_wr_o[1]) # sub wr
+ m.d.comb += go_rd_i[0:2].eq(go_rd_o[0:2]) # add rd
+ m.d.comb += go_wr_i[0:2].eq(go_wr_o[0:2]) # add wr
m.d.comb += intfudeps.issue_i.eq(fn_issue_o)
- # Connect INT Fn Unit global wr/rd pending
- for fu in if_l:
- m.d.comb += fu.g_int_wr_pend_i.eq(g_int_wr_pend_v.g_pend_o)
- m.d.comb += fu.g_int_rd_pend_i.eq(g_int_rd_pend_v.g_pend_o)
+ # Connect INT FU go_rd/wr
+ m.d.comb += intfus.go_rd_i.eq(go_rd_o)
+ m.d.comb += intfus.go_wr_i.eq(go_wr_o)
#---------
# connect fu-dep matrix
#---------
r_go_rd_i = intregdeps.go_rd_i
r_go_wr_i = intregdeps.go_wr_i
- m.d.comb += r_go_rd_i.eq(go_rd_i)
- m.d.comb += r_go_wr_i.eq(go_wr_i)
+ m.d.comb += r_go_rd_i.eq(go_rd_o)
+ m.d.comb += r_go_wr_i.eq(go_wr_o)
m.d.comb += intregdeps.dest_i.eq(regdecode.dest_o)
m.d.comb += intregdeps.src1_i.eq(regdecode.src1_o)
# Connect Picker
#---------
- m.d.comb += intpick1.req_rel_i[0].eq(int_alus[0].req_rel_o)
- m.d.comb += intpick1.req_rel_i[1].eq(int_alus[1].req_rel_o)
+ m.d.comb += intpick1.req_rel_i[0:2].eq(cu.req_rel_o[0:2])
int_readable_o = intfudeps.readable_o
int_writable_o = intfudeps.writable_o
- m.d.comb += intpick1.readable_i[0].eq(int_readable_o[0]) # add rd
- m.d.comb += intpick1.writable_i[0].eq(int_writable_o[0]) # add wr
- m.d.comb += intpick1.readable_i[1].eq(int_readable_o[1]) # sub rd
- m.d.comb += intpick1.writable_i[1].eq(int_writable_o[1]) # sub wr
+ m.d.sync += intpick1.readable_i[0:2].eq(int_readable_o[0:2])
+ m.d.sync += intpick1.writable_i[0:2].eq(int_writable_o[0:2])
#---------
# Connect Register File(s)
#---------
+ print ("intregdeps wen len", len(intregdeps.dest_rsel_o))
m.d.sync += int_dest.wen.eq(intregdeps.dest_rsel_o)
m.d.comb += int_src1.ren.eq(intregdeps.src1_rsel_o)
m.d.comb += int_src2.ren.eq(intregdeps.src2_rsel_o)
- # merge (OR) all integer FU / ALU outputs to a single value
- # bit of a hack: treereduce needs a list with an item named "dest_o"
- dest_o = treereduce(int_alus)
- m.d.comb += int_dest.data_i.eq(dest_o)
+ # connect ALUs to regfule
+ m.d.comb += int_dest.data_i.eq(cu.dest_o)
+ m.d.comb += cu.src1_data_i.eq(int_src1.data_o)
+ m.d.comb += cu.src2_data_i.eq(int_src2.data_o)
- # connect ALUs
- for i, alu in enumerate(int_alus):
- m.d.comb += alu.go_rd_i.eq(if_l[i].go_rd_i)
- m.d.comb += alu.go_wr_i.eq(if_l[i].go_wr_i)
- m.d.comb += alu.issue_i.eq(fn_issue_l[i])
- m.d.comb += alu.src1_i.eq(int_src1.data_o)
- m.d.comb += alu.src2_i.eq(int_src2.data_o)
- m.d.comb += if_l[i].req_rel_i.eq(alu.req_rel_o) # pipe out ready
+ # connect ALU Computation Units
+ m.d.sync += cu.go_rd_i[0:2].eq(go_rd_o[0:2])
+ m.d.sync += cu.go_wr_i[0:2].eq(go_wr_o[0:2])
+ m.d.sync += cu.issue_i[0:2].eq(fn_issue_o[0:2])
+
+ # Connect ALU request release to FUs
+ m.d.sync += intfus.req_rel_i.eq(cu.req_rel_o) # pipe out ready
return m
yield dut.int_store_i.eq(0)
for i in range(1, dut.n_regs):
- yield dut.intregs.regs[i].reg.eq(i)
- alusim.setval(i, i)
+ yield dut.intregs.regs[i].reg.eq(i*2)
+ alusim.setval(i, i*2)
if False:
yield from int_instr(dut, alusim, IADD, 4, 3, 5)
yield from alusim.check(dut)
- for i in range(4):
+ for i in range(1):
src1 = randint(1, dut.n_regs-1)
src2 = randint(1, dut.n_regs-1)
while True:
break
if dest not in [src1, src2]:
break
- src1 = 1
- src2 = 7
- dest = src2
+ #src1 = 7
+ #src2 = 4
+ #dest = 2
op = randint(0, 1)
op = 0
yield
yield
yield from alusim.check(dut)
+ yield from alusim.dump(dut)
def explore_groups(dut):
projects / soc.git / blobdiff