# Int ALUs
add = ALU(self.rwid)
sub = ALU(self.rwid)
- m.submodules.comp1 = comp1 = ComputationUnitNoDelay(self.rwid, 1, add)
- m.submodules.comp2 = comp2 = ComputationUnitNoDelay(self.rwid, 1, sub)
- int_alus = [comp1, comp2]
-
- m.d.comb += comp1.oper_i.eq(Const(0)) # temporary/experiment: op=add
- m.d.comb += comp2.oper_i.eq(Const(1)) # temporary/experiment: op=sub
+ mul = ALU(self.rwid)
+ shf = ALU(self.rwid)
+ m.submodules.comp1 = comp1 = ComputationUnitNoDelay(self.rwid, 2, add)
+ m.submodules.comp2 = comp2 = ComputationUnitNoDelay(self.rwid, 2, sub)
+ m.submodules.comp3 = comp3 = ComputationUnitNoDelay(self.rwid, 2, mul)
+ m.submodules.comp4 = comp4 = ComputationUnitNoDelay(self.rwid, 2, shf)
+ int_alus = [comp1, comp2, comp3, comp4]
+
+ m.d.comb += comp1.oper_i.eq(Const(0, 2)) # op=add
+ m.d.comb += comp2.oper_i.eq(Const(1, 2)) # op=sub
+ m.d.comb += comp3.oper_i.eq(Const(2, 2)) # op=mul
+ m.d.comb += comp4.oper_i.eq(Const(3, 2)) # op=shf
go_rd_l = []
go_wr_l = []
self.reg_enable_i = Signal(reset_less=True) # enable reg decode
self.issue_o = Signal(reset_less=True) # instruction was accepted
+ self.busy_o = Signal(reset_less=True) # at least one CU is busy
def elaborate(self, platform):
m = Module()
fp_src2 = self.fpregs.read_port("src2")
# Int ALUs and Comp Units
- n_int_alus = 2
+ n_int_alus = 4
m.submodules.cu = cu = CompUnits(self.rwid, n_int_alus)
# Int FUs
n_fp_fus = 0 # for now
# Integer Priority Picker 1: Adder + Subtractor
- intpick1 = GroupPicker(2) # picks between add and sub
+ intpick1 = GroupPicker(n_int_fus) # picks between add, sub, mul and shf
m.submodules.intpick1 = intpick1
# INT/FP Issue Unit
]
self.int_insn_i = issueunit.i.insn_i # enabled by instruction decode
- # connect global rd/wr pending vectors
- m.d.comb += issueunit.i.g_wr_pend_i.eq(intfus.g_int_wr_pend_o)
+ # connect global rd/wr pending vector (for WaW detection)
+ m.d.sync += issueunit.i.g_wr_pend_i.eq(intfus.g_int_wr_pend_o)
# TODO: issueunit.f (FP)
# and int function issue / busy arrays, and dest/src1/src2
fn_issue_o = issueunit.i.fn_issue_o
m.d.comb += intfus.fn_issue_i.eq(fn_issue_o)
- # XXX sync, so as to stop a simulation infinite loop
m.d.comb += issueunit.i.busy_i.eq(cu.busy_o)
+ m.d.comb += self.busy_o.eq(cu.busy_o.bool())
#---------
# connect fu-fu matrix
go_wr_o = intpick1.go_wr_o
go_rd_i = intfus.go_rd_i
go_wr_i = intfus.go_wr_i
- m.d.comb += go_rd_i[0:2].eq(go_rd_o[0:2]) # add rd
- m.d.comb += go_wr_i[0:2].eq(go_wr_o[0:2]) # add wr
+ m.d.comb += go_rd_i[0:n_int_fus].eq(go_rd_o[0:n_int_fus]) # rd
+ m.d.comb += go_wr_i[0:n_int_fus].eq(go_wr_o[0:n_int_fus]) # wr
# Connect Picker
#---------
- #m.d.comb += intpick1.rd_rel_i[0:2].eq(~go_rd_i[0:2] & cu.busy_o[0:2])
- m.d.comb += intpick1.rd_rel_i[0:2].eq(cu.rd_rel_o[0:2])
- #m.d.comb += intpick1.go_rd_i[0:2].eq(cu.req_rel_o[0:2])
- m.d.comb += intpick1.req_rel_i[0:2].eq(cu.req_rel_o[0:2])
- int_readable_o = intfus.readable_o
- int_writable_o = intfus.writable_o
- m.d.comb += intpick1.readable_i[0:2].eq(int_readable_o[0:2])
- m.d.comb += intpick1.writable_i[0:2].eq(int_writable_o[0:2])
+ m.d.comb += intpick1.rd_rel_i[0:n_int_fus].eq(cu.rd_rel_o[0:n_int_fus])
+ m.d.comb += intpick1.req_rel_i[0:n_int_fus].eq(cu.req_rel_o[0:n_int_fus])
+ int_rd_o = intfus.readable_o
+ int_wr_o = intfus.writable_o
+ m.d.comb += intpick1.readable_i[0:n_int_fus].eq(int_rd_o[0:n_int_fus])
+ m.d.comb += intpick1.writable_i[0:n_int_fus].eq(int_wr_o[0:n_int_fus])
#---------
# Connect Register File(s)
m.d.comb += cu.src2_data_i.eq(int_src2.data_o)
# connect ALU Computation Units
- m.d.comb += cu.go_rd_i[0:2].eq(go_rd_o[0:2])
- m.d.comb += cu.go_wr_i[0:2].eq(go_wr_o[0:2])
- m.d.comb += cu.issue_i[0:2].eq(fn_issue_o[0:2])
+ m.d.comb += cu.go_rd_i[0:n_int_fus].eq(go_rd_o[0:n_int_fus])
+ m.d.comb += cu.go_wr_i[0:n_int_fus].eq(go_wr_o[0:n_int_fus])
+ m.d.comb += cu.issue_i[0:n_int_fus].eq(fn_issue_o[0:n_int_fus])
return m
IADD = 0
ISUB = 1
+IMUL = 2
+ISHF = 3
class RegSim:
def __init__(self, rwidth, nregs):
src1 = self.regs[src1]
src2 = self.regs[src2]
if op == IADD:
- val = (src1 + src2) & ((1<<(self.rwidth))-1)
+ val = (src1 + src2)
elif op == ISUB:
- val = (src1 - src2) & ((1<<(self.rwidth))-1)
+ val = (src1 - src2)
+ elif op == IMUL:
+ val = (src1 * src2)
+ elif op == ISHF:
+ val = (src1 << (src2 & self.rwidth))
+ val &= ((1<<(self.rwidth))-1)
self.regs[dest] = val
def setval(self, dest, val):
def scoreboard_sim(dut, alusim):
- yield dut.int_store_i.eq(0)
- for i in range(1, dut.n_regs):
- yield dut.intregs.regs[i].reg.eq(4+i*2)
- alusim.setval(i, 4+i*2)
+ yield dut.int_store_i.eq(0)
- instrs = []
- if False:
- for i in range(2):
- src1 = randint(1, dut.n_regs-1)
- src2 = randint(1, dut.n_regs-1)
+ for i in range(1):
+
+ # set random values in the registers
+ for i in range(1, dut.n_regs):
+ yield dut.intregs.regs[i].reg.eq(31+i*3)
+ alusim.setval(i, 31+i*3)
+
+ # create some instructions (some random, some regression tests)
+ instrs = []
+ if False:
+ for i in range(10):
+ src1 = randint(1, dut.n_regs-1)
+ src2 = randint(1, dut.n_regs-1)
+ while True:
+ dest = randint(1, dut.n_regs-1)
+ break
+ if dest not in [src1, src2]:
+ break
+ #src1 = 2
+ #src2 = 3
+ #dest = 2
+
+ op = randint(0, 2)
+ #op = i % 2
+ #op = 0
+
+ instrs.append((src1, src2, dest, op))
+
+ if False:
+ instrs.append((2, 3, 3, 0))
+ instrs.append((5, 3, 3, 1))
+
+ if False:
+ instrs.append((5, 6, 2, 1))
+ instrs.append((2, 2, 4, 0))
+ #instrs.append((2, 2, 3, 1))
+
+ if False:
+ instrs.append((2, 1, 2, 3))
+
+ if False:
+ instrs.append((2, 6, 2, 1))
+ instrs.append((2, 1, 2, 0))
+
+ if False:
+ instrs.append((1, 2, 7, 2))
+ instrs.append((7, 1, 5, 0))
+ instrs.append((4, 4, 1, 1))
+
+ if False:
+ instrs.append((5, 6, 2, 2))
+ instrs.append((1, 1, 4, 1))
+ instrs.append((6, 5, 3, 0))
+
+ if False:
+ # Write-after-Write Hazard
+ instrs.append( (3, 6, 7, 2) )
+ instrs.append( (4, 4, 7, 1) )
+
+ if False:
+ # self-read/write-after-write followed by Read-after-Write
+ instrs.append((1, 1, 1, 1))
+ instrs.append((1, 5, 3, 0))
+
+ if False:
+ # Read-after-Write followed by self-read-after-write
+ instrs.append((5, 6, 1, 2))
+ instrs.append((1, 1, 1, 1))
+
+ if False:
+ # self-read-write sandwich
+ instrs.append((5, 6, 1, 2))
+ instrs.append((1, 1, 1, 1))
+ instrs.append((1, 5, 3, 0))
+
+ if True:
+ instrs.append( (7, 1, 2, 0) )
+ instrs.append( (1, 1, 4, 2) )
+ instrs.append( (2, 3, 2, 2) )
+ instrs.append( (5, 3, 1, 0) )
+ instrs.append( (7, 3, 5, 2) )
+ instrs.append( (1, 2, 6, 2) )
+ instrs.append( (5, 2, 5, 2) )
+ instrs.append( (2, 2, 3, 0) )
+ instrs.append( (4, 2, 2, 1) )
+ instrs.append( (2, 4, 6, 1) )
+
+ # issue instruction(s), wait for issue to be free before proceeding
+ for i, (src1, src2, dest, op) in enumerate(instrs):
+
+ print ("instr %d: (%d, %d, %d, %d)" % (i, src1, src2, dest, op))
+ yield from int_instr(dut, alusim, op, src1, src2, dest)
+ yield
while True:
- dest = randint(1, dut.n_regs-1)
- break
- if dest not in [src1, src2]:
+ issue_o = yield dut.issue_o
+ if issue_o:
+ for i in range(len(dut.int_insn_i)):
+ yield dut.int_insn_i[i].eq(0)
+ yield dut.reg_enable_i.eq(0)
break
- #src1 = 2
- #src2 = 3
- #dest = 2
-
- op = randint(0, 1)
- op = i % 2
- op = 0
- instrs.append((src1, src2, dest, op))
+ #print ("busy",)
+ #yield from print_reg(dut, [1,2,3])
+ yield
+ #yield from print_reg(dut, [1,2,3])
- if False:
- instrs.append((2, 3, 3, 0))
- instrs.append((5, 3, 3, 1))
-
- if True:
- instrs.append((5, 6, 2, 1))
- instrs.append((2, 2, 4, 0))
- #instrs.append((2, 2, 3, 1))
-
- for i, (src1, src2, dest, op) in enumerate(instrs):
-
- print ("instr %d: %d %d %d %d\n" % (i, op, src1, src2, dest))
- yield from int_instr(dut, alusim, op, src1, src2, dest)
+ # wait for all instructions to stop before checking
yield
while True:
- issue_o = yield dut.issue_o
- if issue_o:
- for i in range(len(dut.int_insn_i)):
- yield dut.int_insn_i[i].eq(0)
- yield dut.reg_enable_i.eq(0)
+ busy_o = yield dut.busy_o
+ if not busy_o:
break
print ("busy",)
- yield from print_reg(dut, [1,2,3])
yield
- yield from print_reg(dut, [1,2,3])
- yield
- yield
- yield
- yield
- yield from print_reg(dut, [1,2,3])
- yield
- yield from print_reg(dut, [1,2,3])
- yield
- yield from print_reg(dut, [1,2,3])
- yield
- yield from print_reg(dut, [1,2,3])
- yield
- yield
- yield
- yield
- yield from alusim.check(dut)
- yield from alusim.dump(dut)
+ # check status
+ yield from alusim.check(dut)
+ yield from alusim.dump(dut)
def explore_groups(dut):
projects / soc.git / blobdiff