convert SPRs and others to Data.data/ok

[soc.git] / src / experiment / score6600.py

diff --git a/src/experiment/score6600.py b/src/experiment/score6600.py
index 8a4efae92003432cbba23848c71376319b7a58d4..209bc99c28e8dae05a8e4003c697aac9fbb385a1 100644 (file)
--- a/src/experiment/score6600.py
+++ b/src/experiment/score6600.py
@@ -1,5 +1,6 @@
 from nmigen.compat.sim import run_simulation
 from nmigen.cli import verilog, rtlil
+from nmigen.hdl.ast import unsigned
 from nmigen import Module, Const, Signal, Array, Cat, Elaboratable, Memory
 
 from regfile.regfile import RegFileArray, treereduce
@@ -192,6 +193,8 @@ class CompUnitsBase(Elaboratable):
             stmem_l.append(alu.stwd_mem_o)
             go_ad_l.append(alu.go_ad_i)
             go_st_l.append(alu.go_st_i)
+        comb += self.ld_o.eq(Cat(*ld_l))
+        comb += self.st_o.eq(Cat(*st_l))
         comb += self.adr_rel_o.eq(Cat(*adr_rel_l))
         comb += self.sto_rel_o.eq(Cat(*sto_rel_l))
         comb += self.load_mem_o.eq(Cat(*ldmem_l))
@@ -419,9 +422,9 @@ class Scoreboard(Elaboratable):
         self.ls_imm_i = Signal(rwid, reset_less=True)
 
         # inputs
-        self.int_dest_i = Signal(max=n_regs, reset_less=True) # Dest R# in
-        self.int_src1_i = Signal(max=n_regs, reset_less=True) # oper1 R# in
-        self.int_src2_i = Signal(max=n_regs, reset_less=True) # oper2 R# in
+        self.int_dest_i = Signal(range(n_regs), reset_less=True) # Dest R# in
+        self.int_src1_i = Signal(range(n_regs), reset_less=True) # oper1 R# in
+        self.int_src2_i = Signal(range(n_regs), reset_less=True) # oper2 R# in
         self.reg_enable_i = Signal(reset_less=True) # enable reg decode
 
         # outputs
@@ -575,7 +578,7 @@ class Scoreboard(Elaboratable):
         # XXX should only be done when the memory ld/st has actually happened!
         go_st_i = Signal(cul.n_units, reset_less=True)
         go_ld_i = Signal(cul.n_units, reset_less=True)
-        comb += go_ld_i.eq(memfus.storable_o & memfus.addr_nomatch_o &\
+        comb += go_ld_i.eq(memfus.loadable_o & memfus.addr_nomatch_o &\
                                   cul.req_rel_o & cul.ld_o)
         comb += go_st_i.eq(memfus.storable_o & memfus.addr_nomatch_o &\
                                   cul.sto_rel_o & cul.st_o)
@@ -740,7 +743,7 @@ class IssueToScoreboard(Elaboratable):
         self.opw = opwid
         self.n_regs = n_regs
 
-        mqbits = (int(log(qlen) / log(2))+2, False)
+        mqbits = unsigned(int(log(qlen) / log(2))+2)
         self.p_add_i = Signal(mqbits) # instructions to add (from data_i)
         self.p_ready_o = Signal() # instructions were added
         self.data_i = Instruction.nq(n_in, "data_i", rwid, opwid)
@@ -1145,19 +1148,19 @@ def scoreboard_sim(dut, alusim):
         if False:
             instrs = create_random_ops(dut, 15, True, 4)
 
-        if True: # LD/ST test (with immediate)
-            instrs.append( (1, 2, 2, 0x30, 1, 1, (0, 0)) )
-            #instrs.append( (1, 2, 7, 0x10, 1, 1, (0, 0)) )
+        if False: # LD/ST test (with immediate)
+            instrs.append( (1, 2, 0, 0x10, 1, 1, (0, 0)) )
+            #instrs.append( (1, 2, 0, 0x10, 1, 1, (0, 0)) )
 
-        if False:
+        if True:
             instrs.append( (1, 2, 2, 1, 1, 20, (0, 0)) )
 
-        if False:
-            instrs.append( (7, 3, 2, 4, (0, 0)) )
-            instrs.append( (7, 6, 6, 2, (0, 0)) )
-            instrs.append( (1, 7, 2, 2, (0, 0)) )
+        if True:
+            instrs.append( (7, 3, 2, 4, 0, 0, (0, 0)) )
+            instrs.append( (7, 6, 6, 2, 0, 0, (0, 0)) )
+            instrs.append( (1, 7, 2, 2, 0, 0, (0, 0)) )
 
-        if False:
+        if True:
             instrs.append((2, 3, 3, 0, 0, 0, (0, 0)))
             instrs.append((5, 3, 3, 1, 0, 0, (0, 0)))
             instrs.append((3, 5, 5, 2, 0, 0, (0, 0)))