from scoreboard.global_pending import GlobalPending
from scoreboard.group_picker import GroupPicker
from scoreboard.issue_unit import IntFPIssueUnit, RegDecode
-from scoreboard.shadow import ShadowMatrix
+from scoreboard.shadow import ShadowMatrix, WaWGrid
from compalu import ComputationUnitNoDelay
-from alu_hier import ALU
+from alu_hier import ALU, BranchALU
from nmutil.latch import SRLatch
from random import randint
+
class CompUnits(Elaboratable):
def __init__(self, rwid, n_units):
* :rwid: bit width of register file(s) - both FP and INT
* :n_units: number of ALUs
+
+ Note: bgt unit is returned so that a shadow unit can be created
+ for it
+
"""
self.n_units = n_units
self.rwid = rwid
+ # inputs
self.issue_i = Signal(n_units, reset_less=True)
self.go_rd_i = Signal(n_units, reset_less=True)
self.go_wr_i = Signal(n_units, reset_less=True)
self.shadown_i = Signal(n_units, reset_less=True)
self.go_die_i = Signal(n_units, reset_less=True)
+
+ # outputs
self.busy_o = Signal(n_units, reset_less=True)
self.rd_rel_o = Signal(n_units, reset_less=True)
self.req_rel_o = Signal(n_units, reset_less=True)
+ # in/out register data (note: not register#, actual data)
self.dest_o = Signal(rwid, reset_less=True)
self.src1_data_i = Signal(rwid, reset_less=True)
self.src2_data_i = Signal(rwid, reset_less=True)
+ # Branch ALU
+ self.bgt = BranchALU(self.rwid)
+
def elaborate(self, platform):
m = Module()
sub = ALU(self.rwid)
mul = ALU(self.rwid)
shf = ALU(self.rwid)
+ bgt = self.bgt
+
m.submodules.comp1 = comp1 = ComputationUnitNoDelay(self.rwid, 2, add)
m.submodules.comp2 = comp2 = ComputationUnitNoDelay(self.rwid, 2, sub)
m.submodules.comp3 = comp3 = ComputationUnitNoDelay(self.rwid, 2, mul)
m.submodules.comp4 = comp4 = ComputationUnitNoDelay(self.rwid, 2, shf)
- int_alus = [comp1, comp2, comp3, comp4]
+ m.submodules.br1 = br1 = ComputationUnitNoDelay(self.rwid, 2, bgt)
+ int_alus = [comp1, comp2, comp3, comp4, br1]
m.d.comb += comp1.oper_i.eq(Const(0, 2)) # op=add
m.d.comb += comp2.oper_i.eq(Const(1, 2)) # op=sub
m.d.comb += comp3.oper_i.eq(Const(2, 2)) # op=mul
m.d.comb += comp4.oper_i.eq(Const(3, 2)) # op=shf
+ m.d.comb += br1.oper_i.eq(Const(0, 2)) # op=bgt
go_rd_l = []
go_wr_l = []
self.req_rel_o = Signal(n_int_alus, reset_less=True)
self.fn_issue_i = Signal(n_int_alus, reset_less=True)
+ # Note: FURegs wr_pend_o is also outputted from here, for use in WaWGrid
+
def elaborate(self, platform):
m = Module()
m.d.comb += intfudeps.rd_pend_i.eq(intregdeps.rd_pend_o)
m.d.comb += intfudeps.wr_pend_i.eq(intregdeps.wr_pend_o)
+ self.wr_pend_o = intregdeps.wr_pend_o # also output for use in WaWGrid
m.d.comb += intfudeps.issue_i.eq(self.fn_issue_i)
m.d.comb += intfudeps.go_rd_i.eq(self.go_rd_i)
self.int_src2_i = Signal(max=n_regs, reset_less=True) # oper2 R# in
self.reg_enable_i = Signal(reset_less=True) # enable reg decode
+ # outputs
self.issue_o = Signal(reset_less=True) # instruction was accepted
self.busy_o = Signal(reset_less=True) # at least one CU is busy
+ # for branch speculation experiment. branch_direction = 0 if
+ # the branch hasn't been met yet. 1 indicates "success", 2 is "fail"
+ # branch_succ and branch_fail are requests to have the current
+ # instruction be dependent on the branch unit "shadow" capability.
+ self.branch_succ_i = Signal(reset_less=True)
+ self.branch_fail_i = Signal(reset_less=True)
+ self.branch_direction_o = Signal(2, reset_less=True)
+
def elaborate(self, platform):
m = Module()
m.submodules.intregs = self.intregs
m.submodules.fpregs = self.fpregs
+ # dummy values
+ m.d.sync += self.branch_succ_i.eq(Const(0))
+ m.d.sync += self.branch_fail_i.eq(Const(0))
+ m.d.sync += self.branch_direction_o.eq(Const(0))
+
# register ports
int_dest = self.intregs.write_port("dest")
int_src1 = self.intregs.read_port("src1")
fp_src2 = self.fpregs.read_port("src2")
# Int ALUs and Comp Units
- n_int_alus = 4
+ n_int_alus = 5
m.submodules.cu = cu = CompUnits(self.rwid, n_int_alus)
- m.d.comb += cu.shadown_i.eq(-1)
m.d.comb += cu.go_die_i.eq(0)
+ bgt = cu.bgt # get at the branch computation unit
# Int FUs
m.submodules.intfus = intfus = FunctionUnits(self.n_regs, n_int_alus)
issueunit = IntFPIssueUnit(self.n_regs, n_int_fus, n_fp_fus)
m.submodules.issueunit = issueunit
- # Shadow Matrix. currently only 1 branch
- m.submodules.shadows = shadows = ShadowMatrix(n_int_fus, 1)
+ # Shadow Matrix. currently n_int_fus shadows, to be used for
+ # write-after-write hazards. NOTE: there is one extra for branches,
+ # so the shadow width is increased by 1
+ m.submodules.shadows = shadows = ShadowMatrix(n_int_fus, n_int_fus+1)
+ # combined go_rd/wr + go_die (go_die used to reset latches)
go_rd_rst = Signal(n_int_fus, reset_less=True)
go_wr_rst = Signal(n_int_fus, reset_less=True)
+ # record previous instruction to cast shadow on current instruction
+ fn_issue_prev = Signal(n_int_fus)
+ prev_shadow = Signal(n_int_fus)
#---------
# ok start wiring things together...
# connect fu-fu matrix
#---------
- # Group Picker... done manually for now. TODO: cat array of pick sigs
+ # Group Picker... done manually for now.
go_rd_o = intpick1.go_rd_o
go_wr_o = intpick1.go_wr_o
go_rd_i = intfus.go_rd_i
go_wr_i = intfus.go_wr_i
- m.d.comb += go_rd_i[0:n_int_fus].eq(go_rd_o[0:n_int_fus]) # rd
- m.d.comb += go_wr_i[0:n_int_fus].eq(go_wr_o[0:n_int_fus]) # wr
+ # NOTE: connect to the shadowed versions so that they can "die" (reset)
+ m.d.comb += go_rd_i[0:n_int_fus].eq(go_rd_rst[0:n_int_fus]) # rd
+ m.d.comb += go_wr_i[0:n_int_fus].eq(go_wr_rst[0:n_int_fus]) # wr
# Connect Picker
#---------
m.d.comb += intpick1.readable_i[0:n_int_fus].eq(int_rd_o[0:n_int_fus])
m.d.comb += intpick1.writable_i[0:n_int_fus].eq(int_wr_o[0:n_int_fus])
+ #---------
+ # Shadow Matrix
+ #---------
+
+ m.d.comb += shadows.issue_i.eq(fn_issue_o)
+ # these are explained in ShadowMatrix docstring, and are to be
+ # connected to the FUReg and FUFU Matrices, to get them to reset
+ # NOTE: do NOT connect these to the Computation Units. The CUs need to
+ # do something slightly different (due to the revolving-door SRLatches)
+ m.d.comb += go_rd_rst.eq(go_rd_o | shadows.go_die_o)
+ m.d.comb += go_wr_rst.eq(go_wr_o | shadows.go_die_o)
+
+ # connect shadows / go_dies to Computation Units
+ m.d.comb += cu.shadown_i[0:n_int_fus].eq(shadows.shadown_o[0:n_int_fus])
+ m.d.comb += cu.go_die_i[0:n_int_fus].eq(shadows.go_die_o[0:n_int_fus])
+
+ # ok connect first n_int_fu shadows to busy lines, to create an
+ # instruction-order linked-list-like arrangement, using a bit-matrix
+ # (instead of e.g. a ring buffer).
+ # XXX TODO
+
+ # when written, the shadow can be cancelled (and was good)
+ m.d.comb += shadows.s_good_i[0:n_int_fus].eq(go_wr_o[0:n_int_fus])
+
+ # work out the current-activated busy unit (by recording the old one)
+ with m.If(fn_issue_o): # only update prev bit if instruction issued
+ m.d.sync += fn_issue_prev.eq(fn_issue_o)
+
+ # *previous* instruction shadows *current* instruction, and, obviously,
+ # if the previous is completed (!busy) don't cast the shadow!
+ m.d.comb += prev_shadow.eq(~fn_issue_o & fn_issue_prev & cu.busy_o)
+ for i in range(n_int_fus):
+ m.d.comb += shadows.shadow_i[i][0:n_int_fus].eq(prev_shadow)
+
#---------
# Connect Register File(s)
#---------
yield self.int_src1_i
yield self.int_src2_i
yield self.issue_o
- #yield from self.int_src1
- #yield from self.int_dest
- #yield from self.int_src1
- #yield from self.int_src2
- #yield from self.fp_dest
- #yield from self.fp_src1
- #yield from self.fp_src2
+ yield self.branch_succ_i
+ yield self.branch_fail_i
+ yield self.branch_direction_o
def ports(self):
return list(self)
ISUB = 1
IMUL = 2
ISHF = 3
+IBGT = 4
+IBLT = 5
+IBEQ = 6
+IBNE = 7
class RegSim:
def __init__(self, rwidth, nregs):
def op(self, op, src1, src2, dest):
maxbits = (1 << self.rwidth) - 1
- src1 = self.regs[src1]
- src2 = self.regs[src2]
+ src1 = self.regs[src1] & maxbits
+ src2 = self.regs[src2] & maxbits
if op == IADD:
val = src1 + src2
elif op == ISUB:
val = src1 * src2
elif op == ISHF:
val = src1 >> (src2 & maxbits)
+ elif op == IBGT:
+ val = int(src1 > src2)
+ elif op == IBLT:
+ val = int(src1 < src2)
+ elif op == IBEQ:
+ val = int(src1 == src2)
+ elif op == IBNE:
+ val = int(src1 != src2)
val &= maxbits
self.regs[dest] = val
yield from self.dump(dut)
assert False
-def int_instr(dut, alusim, op, src1, src2, dest):
+def int_instr(dut, op, src1, src2, dest, branch_success, branch_fail):
for i in range(len(dut.int_insn_i)):
yield dut.int_insn_i[i].eq(0)
yield dut.int_dest_i.eq(dest)
yield dut.int_src2_i.eq(src2)
yield dut.int_insn_i[op].eq(1)
yield dut.reg_enable_i.eq(1)
- alusim.op(op, src1, src2, dest)
+
+ # these indicate that the instruction is to be made shadow-dependent on
+ # (either) branch success or branch fail
+ yield dut.branch_fail_i.eq(branch_fail)
+ yield dut.branch_succ_i.eq(branch_success)
def print_reg(dut, rnums):
print ("reg %s: %s" % (','.join(rnums), ','.join(rs)))
+def create_random_ops(n_ops, shadowing=False):
+ insts = []
+ for i in range(n_ops):
+ src1 = randint(1, dut.n_regs-1)
+ src2 = randint(1, dut.n_regs-1)
+ dest = randint(1, dut.n_regs-1)
+ op = randint(0, 3)
+
+ if shadowing:
+ instrs.append((src1, src2, dest, op, (False, False)))
+ else:
+ instrs.append((src1, src2, dest, op))
+ return insts
+
+
+def wait_for_busy_clear(dut):
+ while True:
+ busy_o = yield dut.busy_o
+ if not busy_o:
+ break
+ print ("busy",)
+ yield
+
+
+def wait_for_issue(dut):
+ while True:
+ issue_o = yield dut.issue_o
+ if issue_o:
+ for i in range(len(dut.int_insn_i)):
+ yield dut.int_insn_i[i].eq(0)
+ yield dut.reg_enable_i.eq(0)
+ break
+ #print ("busy",)
+ #yield from print_reg(dut, [1,2,3])
+ yield
+ #yield from print_reg(dut, [1,2,3])
+
+def scoreboard_branch_sim(dut, alusim):
+
+ yield dut.int_store_i.eq(1)
+
+ for i in range(2):
+
+ # set random values in the registers
+ for i in range(1, dut.n_regs):
+ val = 31+i*3
+ val = randint(0, (1<<alusim.rwidth)-1)
+ yield dut.intregs.regs[i].reg.eq(val)
+ alusim.setval(i, val)
+
+ # create some instructions: branches create a tree
+ insts = create_random_ops(5)
+
+ src1 = randint(1, dut.n_regs-1)
+ src2 = randint(1, dut.n_regs-1)
+ op = randint(4, 7)
+
+ branch_ok = create_random_ops(5)
+ branch_fail = create_random_ops(5)
+
+ insts.append((src1, src2, (branch_ok, branch_fail), op, (0, 0)))
+
+ # issue instruction(s)
+ i = -1
+ instrs = insts
+ branch_direction = 0
+ while instrs:
+ i += 1
+ (src1, src2, dest, op, (shadow_on, shadow_off)) = insts.pop()
+ if branch_direction == 1 and shadow_off:
+ continue # branch was "success" and this is a "failed"... skip
+ if branch_direction == 2 and shadow_on:
+ continue # branch was "fail" and this is a "success"... skip
+ is_branch = op >= 4
+ if is_branch:
+ branch_ok, branch_fail = dest
+ dest = None
+ # ok zip up the branch success / fail instructions and
+ # drop them into the queue, one marked "to have branch success"
+ # the other to be marked shadow branch "fail".
+ # one out of each of these will be cancelled
+ for ok, fl in zip(branch_ok, branch_fail):
+ instrs.append((ok[0], ok[1], ok[2], ok[3], (1, 0)))
+ instrs.append((fl[0], fl[1], fl[2], fl[3], (0, 1)))
+ print ("instr %d: (%d, %d, %d, %d)" % (i, src1, src2, dest, op))
+ yield from int_instr(dut, op, src1, src2, dest,
+ shadow_on, shadow_off)
+ yield
+ yield from wait_for_issue(dut)
+ branch_direction = dut.branch_direction_o # which way branch went
+
+ # wait for all instructions to stop before checking
+ yield
+ yield from wait_for_busy_clear(dut)
+
+ for (src1, src2, dest, op, (shadow_on, shadow_off)) in insts:
+ is_branch = op >= 4
+ if is_branch:
+ branch_ok, branch_fail = dest
+ dest = None
+ branch_res = alusim.op(op, src1, src2, dest)
+ if is_branch:
+ if branch_res:
+ insts.append(branch_ok)
+ else:
+ insts.append(branch_fail)
+
+ # check status
+ yield from alusim.check(dut)
+ yield from alusim.dump(dut)
+
+
def scoreboard_sim(dut, alusim):
- yield dut.int_store_i.eq(0)
+ yield dut.int_store_i.eq(1)
- for i in range(1):
+ for i in range(20):
# set random values in the registers
for i in range(1, dut.n_regs):
#src2 = 3
#dest = 2
- op = randint(0, 3)
+ op = randint(0, 4)
#op = i % 2
#op = 0
for i, (src1, src2, dest, op) in enumerate(instrs):
print ("instr %d: (%d, %d, %d, %d)" % (i, src1, src2, dest, op))
- yield from int_instr(dut, alusim, op, src1, src2, dest)
+ alusim.op(op, src1, src2, dest)
+ yield from int_instr(dut, op, src1, src2, dest, 0, 0)
yield
- while True:
- issue_o = yield dut.issue_o
- if issue_o:
- for i in range(len(dut.int_insn_i)):
- yield dut.int_insn_i[i].eq(0)
- yield dut.reg_enable_i.eq(0)
- break
- #print ("busy",)
- #yield from print_reg(dut, [1,2,3])
- yield
- #yield from print_reg(dut, [1,2,3])
+ yield from wait_for_issue(dut)
# wait for all instructions to stop before checking
yield
- while True:
- busy_o = yield dut.busy_o
- if not busy_o:
- break
- print ("busy",)
- yield
+ yield from wait_for_busy_clear(dut)
# check status
yield from alusim.check(dut)
yield from alusim.dump(dut)
-def explore_groups(dut):
- from nmigen.hdl.ir import Fragment
- from nmigen.hdl.xfrm import LHSGroupAnalyzer
-
- fragment = dut.elaborate(platform=None)
- fr = Fragment.get(fragment, platform=None)
-
- groups = LHSGroupAnalyzer()(fragment._statements)
-
- print (groups)
-
-
def test_scoreboard():
dut = Scoreboard(16, 8)
alusim = RegSim(16, 8)
projects / soc.git / blobdiff