from scoreboard.global_pending import GlobalPending
from scoreboard.group_picker import GroupPicker
from scoreboard.issue_unit import IntFPIssueUnit, RegDecode
+from scoreboard.shadow import ShadowMatrix, WaWGrid
from compalu import ComputationUnitNoDelay
self.issue_i = Signal(n_units, reset_less=True)
self.go_rd_i = Signal(n_units, reset_less=True)
self.go_wr_i = Signal(n_units, reset_less=True)
+ self.shadown_i = Signal(n_units, reset_less=True)
+ self.go_die_i = Signal(n_units, reset_less=True)
+ self.busy_o = Signal(n_units, reset_less=True)
+ self.rd_rel_o = Signal(n_units, reset_less=True)
self.req_rel_o = Signal(n_units, reset_less=True)
self.dest_o = Signal(rwid, reset_less=True)
# Int ALUs
add = ALU(self.rwid)
sub = ALU(self.rwid)
- m.submodules.comp1 = comp1 = ComputationUnitNoDelay(self.rwid, 1, add)
- m.submodules.comp2 = comp2 = ComputationUnitNoDelay(self.rwid, 1, sub)
- int_alus = [comp1, comp2]
-
- m.d.comb += comp1.oper_i.eq(Const(0)) # temporary/experiment: op=add
- m.d.comb += comp2.oper_i.eq(Const(1)) # temporary/experiment: op=sub
+ mul = ALU(self.rwid)
+ shf = ALU(self.rwid)
+ m.submodules.comp1 = comp1 = ComputationUnitNoDelay(self.rwid, 2, add)
+ m.submodules.comp2 = comp2 = ComputationUnitNoDelay(self.rwid, 2, sub)
+ m.submodules.comp3 = comp3 = ComputationUnitNoDelay(self.rwid, 2, mul)
+ m.submodules.comp4 = comp4 = ComputationUnitNoDelay(self.rwid, 2, shf)
+ int_alus = [comp1, comp2, comp3, comp4]
+
+ m.d.comb += comp1.oper_i.eq(Const(0, 2)) # op=add
+ m.d.comb += comp2.oper_i.eq(Const(1, 2)) # op=sub
+ m.d.comb += comp3.oper_i.eq(Const(2, 2)) # op=mul
+ m.d.comb += comp4.oper_i.eq(Const(3, 2)) # op=shf
go_rd_l = []
go_wr_l = []
issue_l = []
+ busy_l = []
req_rel_l = []
+ rd_rel_l = []
+ shadow_l = []
+ godie_l = []
for alu in int_alus:
req_rel_l.append(alu.req_rel_o)
+ rd_rel_l.append(alu.rd_rel_o)
+ shadow_l.append(alu.shadown_i)
+ godie_l.append(alu.go_die_i)
go_wr_l.append(alu.go_wr_i)
go_rd_l.append(alu.go_rd_i)
issue_l.append(alu.issue_i)
+ busy_l.append(alu.busy_o)
+ m.d.comb += self.rd_rel_o.eq(Cat(*rd_rel_l))
m.d.comb += self.req_rel_o.eq(Cat(*req_rel_l))
+ m.d.comb += self.busy_o.eq(Cat(*busy_l))
+ m.d.comb += Cat(*godie_l).eq(self.go_die_i)
+ m.d.comb += Cat(*shadow_l).eq(self.shadown_i)
m.d.comb += Cat(*go_wr_l).eq(self.go_wr_i)
m.d.comb += Cat(*go_rd_l).eq(self.go_rd_i)
m.d.comb += Cat(*issue_l).eq(self.issue_i)
return m
+
class FunctionUnits(Elaboratable):
def __init__(self, n_regs, n_int_alus):
self.n_regs = n_regs
self.n_int_alus = n_int_alus
- self.int_dest_i = Signal(max=n_regs, reset_less=True) # Dest R# in
- self.int_src1_i = Signal(max=n_regs, reset_less=True) # oper1 R# in
- self.int_src2_i = Signal(max=n_regs, reset_less=True) # oper2 R# in
+ self.dest_i = Signal(n_regs, reset_less=True) # Dest R# in
+ self.src1_i = Signal(n_regs, reset_less=True) # oper1 R# in
+ self.src2_i = Signal(n_regs, reset_less=True) # oper2 R# in
- self.req_rel_i = Signal(n_int_alus, reset_less = True)
self.g_int_rd_pend_o = Signal(n_regs, reset_less=True)
self.g_int_wr_pend_o = Signal(n_regs, reset_less=True)
+ self.dest_rsel_o = Signal(n_regs, reset_less=True) # dest reg (bot)
+ self.src1_rsel_o = Signal(n_regs, reset_less=True) # src1 reg (bot)
+ self.src2_rsel_o = Signal(n_regs, reset_less=True) # src2 reg (bot)
+
+ self.req_rel_i = Signal(n_int_alus, reset_less = True)
+ self.readable_o = Signal(n_int_alus, reset_less=True)
+ self.writable_o = Signal(n_int_alus, reset_less=True)
+
self.go_rd_i = Signal(n_int_alus, reset_less=True)
self.go_wr_i = Signal(n_int_alus, reset_less=True)
self.req_rel_o = Signal(n_int_alus, reset_less=True)
self.fn_issue_i = Signal(n_int_alus, reset_less=True)
- self.fn_busy_o = Signal(n_int_alus, reset_less=True)
+
+ # Note: FURegs wr_pend_o is also outputted from here, for use in WaWGrid
def elaborate(self, platform):
m = Module()
- # Int FUs
- if_l = []
- int_src1_pend_v = []
- int_src2_pend_v = []
- int_rd_pend_v = []
- int_wr_pend_v = []
- for i in range(self.n_int_alus):
- # set up Integer Function Unit, add to module (and python list)
- fu = IntFnUnit(self.n_regs, shadow_wid=0)
- setattr(m.submodules, "intfu%d" % i, fu)
- if_l.append(fu)
- # collate the read/write pending vectors (to go into global pending)
- int_src1_pend_v.append(fu.src1_pend_o)
- int_src2_pend_v.append(fu.src2_pend_o)
- int_rd_pend_v.append(fu.int_rd_pend_o)
- int_wr_pend_v.append(fu.int_wr_pend_o)
- int_fus = Array(if_l)
-
- # Global Pending Vectors (INT and TODO FP)
- # NOTE: number of vectors is NOT same as number of FUs.
- g_int_src1_pend_v = GlobalPending(self.n_regs, int_src1_pend_v)
- g_int_src2_pend_v = GlobalPending(self.n_regs, int_src2_pend_v)
- g_int_rd_pend_v = GlobalPending(self.n_regs, int_rd_pend_v)
- g_int_wr_pend_v = GlobalPending(self.n_regs, int_wr_pend_v)
- m.submodules.g_int_src1_pend_v = g_int_src1_pend_v
- m.submodules.g_int_src2_pend_v = g_int_src2_pend_v
- m.submodules.g_int_rd_pend_v = g_int_rd_pend_v
- m.submodules.g_int_wr_pend_v = g_int_wr_pend_v
-
- m.d.comb += self.g_int_rd_pend_o.eq(g_int_rd_pend_v.g_pend_o)
- m.d.comb += self.g_int_wr_pend_o.eq(g_int_wr_pend_v.g_pend_o)
-
- # Connect INT Fn Unit global wr/rd pending
- for fu in if_l:
- m.d.comb += fu.g_int_wr_pend_i.eq(g_int_wr_pend_v.g_pend_o)
- m.d.comb += fu.g_int_rd_pend_i.eq(g_int_rd_pend_v.g_pend_o)
-
- # Connect function issue / busy arrays, and dest/src1/src2
- fn_busy_l = []
- fn_issue_l = []
- req_rel_l = []
- go_rd_l = []
- go_wr_l = []
- for i, fu in enumerate(if_l):
- fn_issue_l.append(fu.issue_i)
- fn_busy_l.append(fu.busy_o)
- go_wr_l.append(fu.go_wr_i)
- go_rd_l.append(fu.go_rd_i)
- req_rel_l.append(fu.req_rel_i)
-
- m.d.comb += fu.dest_i.eq(self.int_dest_i)
- m.d.comb += fu.src1_i.eq(self.int_src1_i)
- m.d.comb += fu.src2_i.eq(self.int_src2_i)
-
- m.d.comb += Cat(*req_rel_l).eq(self.req_rel_i)
- m.d.comb += Cat(*fn_issue_l).eq(self.fn_issue_i)
- m.d.comb += self.fn_busy_o.eq(Cat(*fn_busy_l))
- m.d.comb += Cat(*go_wr_l).eq(self.go_wr_i)
- m.d.comb += Cat(*go_rd_l).eq(self.go_rd_i)
+ n_int_fus = self.n_int_alus
+
+ # Integer FU-FU Dep Matrix
+ intfudeps = FUFUDepMatrix(n_int_fus, n_int_fus)
+ m.submodules.intfudeps = intfudeps
+ # Integer FU-Reg Dep Matrix
+ intregdeps = FURegDepMatrix(n_int_fus, self.n_regs)
+ m.submodules.intregdeps = intregdeps
+
+ m.d.comb += self.g_int_rd_pend_o.eq(intregdeps.rd_rsel_o)
+ m.d.comb += self.g_int_wr_pend_o.eq(intregdeps.wr_rsel_o)
+
+ m.d.comb += intregdeps.rd_pend_i.eq(intregdeps.rd_rsel_o)
+ m.d.comb += intregdeps.wr_pend_i.eq(intregdeps.wr_rsel_o)
+
+ m.d.comb += intfudeps.rd_pend_i.eq(intregdeps.rd_pend_o)
+ m.d.comb += intfudeps.wr_pend_i.eq(intregdeps.wr_pend_o)
+ self.wr_pend_o = intregdeps.wr_pend_o # also output for use in WaWGrid
+ m.d.comb += intfudeps.issue_i.eq(self.fn_issue_i)
+ m.d.comb += intfudeps.go_rd_i.eq(self.go_rd_i)
+ m.d.comb += intfudeps.go_wr_i.eq(self.go_wr_i)
+ m.d.comb += self.readable_o.eq(intfudeps.readable_o)
+ m.d.comb += self.writable_o.eq(intfudeps.writable_o)
+
+ # Connect function issue / arrays, and dest/src1/src2
+ m.d.comb += intregdeps.dest_i.eq(self.dest_i)
+ m.d.comb += intregdeps.src1_i.eq(self.src1_i)
+ m.d.comb += intregdeps.src2_i.eq(self.src2_i)
+
+ m.d.comb += intregdeps.go_rd_i.eq(self.go_rd_i)
+ m.d.comb += intregdeps.go_wr_i.eq(self.go_wr_i)
+ m.d.comb += intregdeps.issue_i.eq(self.fn_issue_i)
+
+ m.d.comb += self.dest_rsel_o.eq(intregdeps.dest_rsel_o)
+ m.d.comb += self.src1_rsel_o.eq(intregdeps.src1_rsel_o)
+ m.d.comb += self.src2_rsel_o.eq(intregdeps.src2_rsel_o)
return m
self.int_dest_i = Signal(max=n_regs, reset_less=True) # Dest R# in
self.int_src1_i = Signal(max=n_regs, reset_less=True) # oper1 R# in
self.int_src2_i = Signal(max=n_regs, reset_less=True) # oper2 R# in
+ self.reg_enable_i = Signal(reset_less=True) # enable reg decode
self.issue_o = Signal(reset_less=True) # instruction was accepted
+ self.busy_o = Signal(reset_less=True) # at least one CU is busy
def elaborate(self, platform):
m = Module()
fp_src2 = self.fpregs.read_port("src2")
# Int ALUs and Comp Units
- n_int_alus = 2
+ n_int_alus = 4
m.submodules.cu = cu = CompUnits(self.rwid, n_int_alus)
+ m.d.comb += cu.go_die_i.eq(0)
# Int FUs
m.submodules.intfus = intfus = FunctionUnits(self.n_regs, n_int_alus)
n_int_fus = n_int_alus
n_fp_fus = 0 # for now
- n_fus = n_int_fus + n_fp_fus # plus FP FUs
-
- # Integer FU-FU Dep Matrix
- intfudeps = FUFUDepMatrix(n_int_fus, n_int_fus)
- m.submodules.intfudeps = intfudeps
- # Integer FU-Reg Dep Matrix
- intregdeps = FURegDepMatrix(n_int_fus, self.n_regs)
- m.submodules.intregdeps = intregdeps
-
# Integer Priority Picker 1: Adder + Subtractor
- intpick1 = GroupPicker(2) # picks between add and sub
+ intpick1 = GroupPicker(n_int_fus) # picks between add, sub, mul and shf
m.submodules.intpick1 = intpick1
# INT/FP Issue Unit
issueunit = IntFPIssueUnit(self.n_regs, n_int_fus, n_fp_fus)
m.submodules.issueunit = issueunit
+ # Shadow Matrix. currently n_int_fus shadows, to be used for
+ # write-after-write hazards
+ m.submodules.shadows = shadows = ShadowMatrix(n_int_fus, n_int_fus)
+ go_rd_rst = Signal(n_int_fus, reset_less=True)
+ go_wr_rst = Signal(n_int_fus, reset_less=True)
+
+ # Write-after-Write grid: selects one shadow to enable, based
+ # on which unit(s) have writes pending and the current instruction
+ # also needing to write
+ m.submodules.wawgrid = wawgrid = WaWGrid(n_int_fus, n_int_fus)
+ busy_prev = Signal(n_int_fus)
+ busy_curr = Signal(n_int_fus)
+ busy_prevbit = Signal(n_int_fus)
+
#---------
# ok start wiring things together...
# "now hear de word of de looord... dem bones dem bones dem dryy bones"
regdecode.dest_i.eq(self.int_dest_i),
regdecode.src1_i.eq(self.int_src1_i),
regdecode.src2_i.eq(self.int_src2_i),
- regdecode.enable_i.eq(1),
+ regdecode.enable_i.eq(self.reg_enable_i),
issueunit.i.dest_i.eq(regdecode.dest_o),
self.issue_o.eq(issueunit.issue_o)
]
self.int_insn_i = issueunit.i.insn_i # enabled by instruction decode
- # connect global rd/wr pending vectors
- m.d.comb += issueunit.i.g_wr_pend_i.eq(intfus.g_int_wr_pend_o)
+ # connect global rd/wr pending vector (for WaW detection)
+ m.d.sync += issueunit.i.g_wr_pend_i.eq(intfus.g_int_wr_pend_o)
# TODO: issueunit.f (FP)
# and int function issue / busy arrays, and dest/src1/src2
- m.d.sync += intfus.int_dest_i.eq(self.int_dest_i)
- m.d.sync += intfus.int_src1_i.eq(self.int_src1_i)
- m.d.sync += intfus.int_src2_i.eq(self.int_src2_i)
+ m.d.comb += intfus.dest_i.eq(regdecode.dest_o)
+ m.d.comb += intfus.src1_i.eq(regdecode.src1_o)
+ m.d.comb += intfus.src2_i.eq(regdecode.src2_o)
- fn_issue_o = Signal(n_int_fus, reset_less=True)
- for i in range(n_int_fus):
- m.d.sync += fn_issue_o[i].eq(issueunit.i.fn_issue_o[i])
+ fn_issue_o = issueunit.i.fn_issue_o
m.d.comb += intfus.fn_issue_i.eq(fn_issue_o)
- # XXX sync, so as to stop a simulation infinite loop
- for i in range(n_int_fus):
- m.d.sync += issueunit.i.busy_i[i].eq(intfus.fn_busy_o[i])
+ m.d.comb += issueunit.i.busy_i.eq(cu.busy_o)
+ m.d.comb += self.busy_o.eq(cu.busy_o.bool())
#---------
# connect fu-fu matrix
#---------
- m.d.comb += intfudeps.rd_pend_i.eq(intfus.g_int_rd_pend_o)
- m.d.comb += intfudeps.wr_pend_i.eq(intfus.g_int_wr_pend_o)
-
- # Group Picker... done manually for now. TODO: cat array of pick sigs
+ # Group Picker... done manually for now.
go_rd_o = intpick1.go_rd_o
go_wr_o = intpick1.go_wr_o
- go_rd_i = intfudeps.go_rd_i
- go_wr_i = intfudeps.go_wr_i
- m.d.comb += go_rd_i[0].eq(go_rd_o[0]) # add rd
- m.d.comb += go_wr_i[0].eq(go_wr_o[0]) # add wr
-
- m.d.comb += go_rd_i[1].eq(go_rd_o[1]) # sub rd
- m.d.comb += go_wr_i[1].eq(go_wr_o[1]) # sub wr
+ go_rd_i = intfus.go_rd_i
+ go_wr_i = intfus.go_wr_i
+ # NOTE: connect to the shadowed versions so that they can "die" (reset)
+ m.d.comb += go_rd_i[0:n_int_fus].eq(go_rd_rst[0:n_int_fus]) # rd
+ m.d.comb += go_wr_i[0:n_int_fus].eq(go_wr_rst[0:n_int_fus]) # wr
- m.d.comb += intfudeps.issue_i.eq(fn_issue_o)
-
- # Connect INT FU go_rd/wr
- m.d.comb += intfus.go_rd_i.eq(go_rd_o)
- m.d.comb += intfus.go_wr_i.eq(go_wr_o)
+ # Connect Picker
+ #---------
+ m.d.comb += intpick1.rd_rel_i[0:n_int_fus].eq(cu.rd_rel_o[0:n_int_fus])
+ m.d.comb += intpick1.req_rel_i[0:n_int_fus].eq(cu.req_rel_o[0:n_int_fus])
+ int_rd_o = intfus.readable_o
+ int_wr_o = intfus.writable_o
+ m.d.comb += intpick1.readable_i[0:n_int_fus].eq(int_rd_o[0:n_int_fus])
+ m.d.comb += intpick1.writable_i[0:n_int_fus].eq(int_wr_o[0:n_int_fus])
#---------
- # connect fu-dep matrix
+ # Shadow Matrix
#---------
- r_go_rd_i = intregdeps.go_rd_i
- r_go_wr_i = intregdeps.go_wr_i
- m.d.comb += r_go_rd_i.eq(go_rd_o)
- m.d.comb += r_go_wr_i.eq(go_wr_o)
-
- m.d.comb += intregdeps.dest_i.eq(regdecode.dest_o)
- m.d.comb += intregdeps.src1_i.eq(regdecode.src1_o)
- m.d.comb += intregdeps.src2_i.eq(regdecode.src2_o)
- m.d.comb += intregdeps.issue_i.eq(fn_issue_o)
- # Connect Picker
- #---------
- m.d.sync += intpick1.req_rel_i[0].eq(cu.req_rel_o[0])
- m.d.sync += intpick1.req_rel_i[1].eq(cu.req_rel_o[1])
- int_readable_o = intfudeps.readable_o
- int_writable_o = intfudeps.writable_o
- m.d.comb += intpick1.readable_i[0].eq(int_readable_o[0]) # add rd
- m.d.comb += intpick1.writable_i[0].eq(int_writable_o[0]) # add wr
- m.d.comb += intpick1.readable_i[1].eq(int_readable_o[1]) # sub rd
- m.d.comb += intpick1.writable_i[1].eq(int_writable_o[1]) # sub wr
+ m.d.comb += shadows.issue_i.eq(fn_issue_o)
+ # these are explained in ShadowMatrix docstring, and are to be
+ # connected to the FUReg and FUFU Matrices, to get them to reset
+ # NOTE: do NOT connect these to the Computation Units. The CUs need to
+ # do something slightly different (due to the revolving-door SRLatches)
+ m.d.comb += go_rd_rst.eq(go_rd_o | shadows.go_die_o)
+ m.d.comb += go_wr_rst.eq(go_wr_o | shadows.go_die_o)
+
+ # connect shadows / go_dies to Computation Units
+ m.d.comb += cu.shadown_i[0:n_int_fus].eq(shadows.shadown_o[0:n_int_fus])
+ m.d.comb += cu.go_die_i[0:n_int_fus].eq(shadows.go_die_o[0:n_int_fus])
+
+ # ok connect first n_int_fu shadows to busy lines, to create an
+ # instruction-order linked-list-like arrangement, using a bit-matrix
+ # (instead of e.g. a ring buffer).
+ # XXX TODO
+
+ # when written, the shadow can be cancelled (and was good)
+ m.d.comb += shadows.s_good_i[0:n_int_fus].eq(go_wr_o[0:n_int_fus])
+
+ # work out the current-activated busy unit (by recording the old one)
+ m.d.sync += busy_prev.eq(cu.busy_o)
+ m.d.comb += busy_curr.eq(~busy_prev & cu.busy_o)
+
+ # now the "2D-bit-array-linked-list" can be created, with the
+ # relationships of the previous and current instruction.
+ # *previous* instruction (busy_prev) shadows *current* instruction
+ #m.d.comb += wawgrid.shadow_i.eq(cu.busy_o & ~fn_issue_o)
+ #m.d.comb += wawgrid.fu_i.eq(fn_issue_o)
+
+ # and now we can connect the wawgrid to the shadow matrix. whewww
+ for i in range(n_int_fus):
+ m.d.comb += shadows.shadow_i[i].eq(wawgrid.waw_o[i])
#---------
# Connect Register File(s)
#---------
- print ("intregdeps wen len", len(intregdeps.dest_rsel_o))
- m.d.comb += int_dest.wen.eq(intregdeps.dest_rsel_o)
- m.d.comb += int_src1.ren.eq(intregdeps.src1_rsel_o)
- m.d.comb += int_src2.ren.eq(intregdeps.src2_rsel_o)
+ print ("intregdeps wen len", len(intfus.dest_rsel_o))
+ m.d.comb += int_dest.wen.eq(intfus.dest_rsel_o)
+ m.d.comb += int_src1.ren.eq(intfus.src1_rsel_o)
+ m.d.comb += int_src2.ren.eq(intfus.src2_rsel_o)
# connect ALUs to regfule
m.d.comb += int_dest.data_i.eq(cu.dest_o)
m.d.comb += cu.src2_data_i.eq(int_src2.data_o)
# connect ALU Computation Units
- for i in range(n_int_alus):
- m.d.comb += cu.go_rd_i[i].eq(go_rd_o[i])
- m.d.comb += cu.go_wr_i[i].eq(go_wr_o[i])
- m.d.comb += cu.issue_i[i].eq(fn_issue_o[i])
-
- # Connect ALU request release to FUs
- m.d.sync += intfus.req_rel_i.eq(cu.req_rel_o) # pipe out ready
+ m.d.comb += cu.go_rd_i[0:n_int_fus].eq(go_rd_o[0:n_int_fus])
+ m.d.comb += cu.go_wr_i[0:n_int_fus].eq(go_wr_o[0:n_int_fus])
+ m.d.comb += cu.issue_i[0:n_int_fus].eq(fn_issue_o[0:n_int_fus])
return m
IADD = 0
ISUB = 1
+IMUL = 2
+ISHF = 3
class RegSim:
def __init__(self, rwidth, nregs):
self.regs = [0] * nregs
def op(self, op, src1, src2, dest):
+ maxbits = (1 << self.rwidth) - 1
src1 = self.regs[src1]
src2 = self.regs[src2]
if op == IADD:
- val = (src1 + src2) & ((1<<(self.rwidth))-1)
+ val = src1 + src2
elif op == ISUB:
- val = (src1 - src2) & ((1<<(self.rwidth))-1)
+ val = src1 - src2
+ elif op == IMUL:
+ val = src1 * src2
+ elif op == ISHF:
+ val = src1 >> (src2 & maxbits)
+ val &= maxbits
self.regs[dest] = val
def setval(self, dest, val):
yield dut.int_src1_i.eq(src1)
yield dut.int_src2_i.eq(src2)
yield dut.int_insn_i[op].eq(1)
+ yield dut.reg_enable_i.eq(1)
alusim.op(op, src1, src2, dest)
def scoreboard_sim(dut, alusim):
- yield dut.int_store_i.eq(0)
-
- for i in range(1, dut.n_regs):
- yield dut.intregs.regs[i].reg.eq(i*2)
- alusim.setval(i, i*2)
- yield
- yield
+ yield dut.int_store_i.eq(0)
- if False:
- yield from int_instr(dut, alusim, IADD, 4, 3, 5)
- yield from print_reg(dut, [3,4,5])
- yield
- yield from int_instr(dut, alusim, IADD, 5, 2, 5)
- yield from print_reg(dut, [3,4,5])
- yield
- yield from int_instr(dut, alusim, ISUB, 5, 1, 3)
- yield from print_reg(dut, [3,4,5])
+ for i in range(10):
+
+ # set random values in the registers
+ for i in range(1, dut.n_regs):
+ val = 31+i*3
+ val = randint(0, (1<<alusim.rwidth)-1)
+ yield dut.intregs.regs[i].reg.eq(val)
+ alusim.setval(i, val)
+
+ # create some instructions (some random, some regression tests)
+ instrs = []
+ if True:
+ for i in range(10):
+ src1 = randint(1, dut.n_regs-1)
+ src2 = randint(1, dut.n_regs-1)
+ while True:
+ dest = randint(1, dut.n_regs-1)
+ break
+ if dest not in [src1, src2]:
+ break
+ #src1 = 2
+ #src2 = 3
+ #dest = 2
+
+ op = randint(0, 3)
+ #op = i % 2
+ #op = 0
+
+ instrs.append((src1, src2, dest, op))
+
+ if False:
+ instrs.append((2, 3, 3, 0))
+ instrs.append((5, 3, 3, 1))
+
+ if False:
+ instrs.append((5, 6, 2, 1))
+ instrs.append((2, 2, 4, 0))
+ #instrs.append((2, 2, 3, 1))
+
+ if False:
+ instrs.append((2, 1, 2, 3))
+
+ if False:
+ instrs.append((2, 6, 2, 1))
+ instrs.append((2, 1, 2, 0))
+
+ if False:
+ instrs.append((1, 2, 7, 2))
+ instrs.append((7, 1, 5, 0))
+ instrs.append((4, 4, 1, 1))
+
+ if False:
+ instrs.append((5, 6, 2, 2))
+ instrs.append((1, 1, 4, 1))
+ instrs.append((6, 5, 3, 0))
+
+ if False:
+ # Write-after-Write Hazard
+ instrs.append( (3, 6, 7, 2) )
+ instrs.append( (4, 4, 7, 1) )
+
+ if False:
+ # self-read/write-after-write followed by Read-after-Write
+ instrs.append((1, 1, 1, 1))
+ instrs.append((1, 5, 3, 0))
+
+ if False:
+ # Read-after-Write followed by self-read-after-write
+ instrs.append((5, 6, 1, 2))
+ instrs.append((1, 1, 1, 1))
+
+ if False:
+ # self-read-write sandwich
+ instrs.append((5, 6, 1, 2))
+ instrs.append((1, 1, 1, 1))
+ instrs.append((1, 5, 3, 0))
+
+ if False:
+ # very weird failure
+ instrs.append( (5, 2, 5, 2) )
+ instrs.append( (2, 6, 3, 0) )
+ instrs.append( (4, 2, 2, 1) )
+
+ # issue instruction(s), wait for issue to be free before proceeding
+ for i, (src1, src2, dest, op) in enumerate(instrs):
+
+ print ("instr %d: (%d, %d, %d, %d)" % (i, src1, src2, dest, op))
+ yield from int_instr(dut, alusim, op, src1, src2, dest)
+ yield
+ while True:
+ issue_o = yield dut.issue_o
+ if issue_o:
+ for i in range(len(dut.int_insn_i)):
+ yield dut.int_insn_i[i].eq(0)
+ yield dut.reg_enable_i.eq(0)
+ break
+ #print ("busy",)
+ #yield from print_reg(dut, [1,2,3])
+ yield
+ #yield from print_reg(dut, [1,2,3])
+
+ # wait for all instructions to stop before checking
yield
- for i in range(len(dut.int_insn_i)):
- yield dut.int_insn_i[i].eq(0)
- yield from print_reg(dut, [3,4,5])
- yield
- yield from print_reg(dut, [3,4,5])
- yield
- yield from print_reg(dut, [3,4,5])
- yield
-
- yield from alusim.check(dut)
-
- for i in range(1):
- src1 = randint(1, dut.n_regs-1)
- src2 = randint(1, dut.n_regs-1)
while True:
- dest = randint(1, dut.n_regs-1)
- break
- if dest not in [src1, src2]:
+ busy_o = yield dut.busy_o
+ if not busy_o:
break
- src1 = 1
- src2 = 4
- dest = 1
-
- op = randint(0, 1)
- op = 0
- print ("random %d: %d %d %d %d\n" % (i, op, src1, src2, dest))
- yield from int_instr(dut, alusim, op, src1, src2, dest)
- yield from print_reg(dut, [3,4,5])
- yield
- yield from print_reg(dut, [3,4,5])
- for i in range(len(dut.int_insn_i)):
- yield dut.int_insn_i[i].eq(0)
- yield
- yield
- yield
+ print ("busy",)
+ yield
-
- yield
- yield from print_reg(dut, [3,4,5])
- yield
- yield from print_reg(dut, [3,4,5])
- yield
- yield
- yield
- yield
- yield from alusim.check(dut)
- yield from alusim.dump(dut)
+ # check status
+ yield from alusim.check(dut)
+ yield from alusim.dump(dut)
def explore_groups(dut):
def test_scoreboard():
- dut = Scoreboard(32, 8)
- alusim = RegSim(32, 8)
+ dut = Scoreboard(16, 8)
+ alusim = RegSim(16, 8)
vl = rtlil.convert(dut, ports=dut.ports())
with open("test_scoreboard6600.il", "w") as f:
f.write(vl)
projects / soc.git / blobdiff