from nmigen import Module, Const, Signal, Array, Cat, Elaboratable
from regfile.regfile import RegFileArray, treereduce
-from scoreboard.fn_unit import IntFnUnit, FPFnUnit, LDFnUnit, STFnUnit
from scoreboard.fu_fu_matrix import FUFUDepMatrix
from scoreboard.fu_reg_matrix import FURegDepMatrix
from scoreboard.global_pending import GlobalPending
from scoreboard.group_picker import GroupPicker
from scoreboard.issue_unit import IntFPIssueUnit, RegDecode
-from scoreboard.shadow import ShadowMatrix, WaWGrid
+from scoreboard.shadow import ShadowMatrix, BranchSpeculationRecord
from compalu import ComputationUnitNoDelay
-from alu_hier import ALU
+from alu_hier import ALU, BranchALU
from nmutil.latch import SRLatch
-from random import randint
+from random import randint, seed
class CompUnits(Elaboratable):
* :rwid: bit width of register file(s) - both FP and INT
* :n_units: number of ALUs
+
+ Note: bgt unit is returned so that a shadow unit can be created
+ for it
+
"""
self.n_units = n_units
self.rwid = rwid
+ # inputs
self.issue_i = Signal(n_units, reset_less=True)
self.go_rd_i = Signal(n_units, reset_less=True)
self.go_wr_i = Signal(n_units, reset_less=True)
self.shadown_i = Signal(n_units, reset_less=True)
self.go_die_i = Signal(n_units, reset_less=True)
+
+ # outputs
self.busy_o = Signal(n_units, reset_less=True)
self.rd_rel_o = Signal(n_units, reset_less=True)
self.req_rel_o = Signal(n_units, reset_less=True)
+ # in/out register data (note: not register#, actual data)
self.dest_o = Signal(rwid, reset_less=True)
self.src1_data_i = Signal(rwid, reset_less=True)
self.src2_data_i = Signal(rwid, reset_less=True)
+ # Branch ALU and CU
+ self.bgt = BranchALU(self.rwid)
+ self.br1 = ComputationUnitNoDelay(self.rwid, 2, self.bgt)
+
def elaborate(self, platform):
m = Module()
+ comb = m.d.comb
+ sync = m.d.sync
# Int ALUs
add = ALU(self.rwid)
sub = ALU(self.rwid)
mul = ALU(self.rwid)
shf = ALU(self.rwid)
+ bgt = self.bgt
+
m.submodules.comp1 = comp1 = ComputationUnitNoDelay(self.rwid, 2, add)
m.submodules.comp2 = comp2 = ComputationUnitNoDelay(self.rwid, 2, sub)
m.submodules.comp3 = comp3 = ComputationUnitNoDelay(self.rwid, 2, mul)
m.submodules.comp4 = comp4 = ComputationUnitNoDelay(self.rwid, 2, shf)
- int_alus = [comp1, comp2, comp3, comp4]
+ m.submodules.br1 = br1 = self.br1
+ int_alus = [comp1, comp2, comp3, comp4, br1]
- m.d.comb += comp1.oper_i.eq(Const(0, 2)) # op=add
- m.d.comb += comp2.oper_i.eq(Const(1, 2)) # op=sub
- m.d.comb += comp3.oper_i.eq(Const(2, 2)) # op=mul
- m.d.comb += comp4.oper_i.eq(Const(3, 2)) # op=shf
+ comb += comp1.oper_i.eq(Const(0, 2)) # op=add
+ comb += comp2.oper_i.eq(Const(1, 2)) # op=sub
+ comb += comp3.oper_i.eq(Const(2, 2)) # op=mul
+ comb += comp4.oper_i.eq(Const(3, 2)) # op=shf
+ comb += br1.oper_i.eq(Const(0, 2)) # op=bgt
go_rd_l = []
go_wr_l = []
go_rd_l.append(alu.go_rd_i)
issue_l.append(alu.issue_i)
busy_l.append(alu.busy_o)
- m.d.comb += self.rd_rel_o.eq(Cat(*rd_rel_l))
- m.d.comb += self.req_rel_o.eq(Cat(*req_rel_l))
- m.d.comb += self.busy_o.eq(Cat(*busy_l))
- m.d.comb += Cat(*godie_l).eq(self.go_die_i)
- m.d.comb += Cat(*shadow_l).eq(self.shadown_i)
- m.d.comb += Cat(*go_wr_l).eq(self.go_wr_i)
- m.d.comb += Cat(*go_rd_l).eq(self.go_rd_i)
- m.d.comb += Cat(*issue_l).eq(self.issue_i)
+ comb += self.rd_rel_o.eq(Cat(*rd_rel_l))
+ comb += self.req_rel_o.eq(Cat(*req_rel_l))
+ comb += self.busy_o.eq(Cat(*busy_l))
+ comb += Cat(*godie_l).eq(self.go_die_i)
+ comb += Cat(*shadow_l).eq(self.shadown_i)
+ comb += Cat(*go_wr_l).eq(self.go_wr_i)
+ comb += Cat(*go_rd_l).eq(self.go_rd_i)
+ comb += Cat(*issue_l).eq(self.issue_i)
# connect data register input/output
# merge (OR) all integer FU / ALU outputs to a single value
# bit of a hack: treereduce needs a list with an item named "dest_o"
dest_o = treereduce(int_alus)
- m.d.comb += self.dest_o.eq(dest_o)
+ comb += self.dest_o.eq(dest_o)
for i, alu in enumerate(int_alus):
- m.d.comb += alu.src1_i.eq(self.src1_data_i)
- m.d.comb += alu.src2_i.eq(self.src2_data_i)
+ comb += alu.src1_i.eq(self.src1_data_i)
+ comb += alu.src2_i.eq(self.src2_data_i)
return m
def elaborate(self, platform):
m = Module()
+ comb = m.d.comb
+ sync = m.d.sync
n_int_fus = self.n_int_alus
intregdeps = FURegDepMatrix(n_int_fus, self.n_regs)
m.submodules.intregdeps = intregdeps
- m.d.comb += self.g_int_rd_pend_o.eq(intregdeps.rd_rsel_o)
- m.d.comb += self.g_int_wr_pend_o.eq(intregdeps.wr_rsel_o)
+ comb += self.g_int_rd_pend_o.eq(intregdeps.rd_rsel_o)
+ comb += self.g_int_wr_pend_o.eq(intregdeps.wr_rsel_o)
- m.d.comb += intregdeps.rd_pend_i.eq(intregdeps.rd_rsel_o)
- m.d.comb += intregdeps.wr_pend_i.eq(intregdeps.wr_rsel_o)
+ comb += intregdeps.rd_pend_i.eq(intregdeps.rd_rsel_o)
+ comb += intregdeps.wr_pend_i.eq(intregdeps.wr_rsel_o)
- m.d.comb += intfudeps.rd_pend_i.eq(intregdeps.rd_pend_o)
- m.d.comb += intfudeps.wr_pend_i.eq(intregdeps.wr_pend_o)
+ comb += intfudeps.rd_pend_i.eq(intregdeps.rd_pend_o)
+ comb += intfudeps.wr_pend_i.eq(intregdeps.wr_pend_o)
self.wr_pend_o = intregdeps.wr_pend_o # also output for use in WaWGrid
- m.d.comb += intfudeps.issue_i.eq(self.fn_issue_i)
- m.d.comb += intfudeps.go_rd_i.eq(self.go_rd_i)
- m.d.comb += intfudeps.go_wr_i.eq(self.go_wr_i)
- m.d.comb += self.readable_o.eq(intfudeps.readable_o)
- m.d.comb += self.writable_o.eq(intfudeps.writable_o)
+ comb += intfudeps.issue_i.eq(self.fn_issue_i)
+ comb += intfudeps.go_rd_i.eq(self.go_rd_i)
+ comb += intfudeps.go_wr_i.eq(self.go_wr_i)
+ comb += self.readable_o.eq(intfudeps.readable_o)
+ comb += self.writable_o.eq(intfudeps.writable_o)
# Connect function issue / arrays, and dest/src1/src2
- m.d.comb += intregdeps.dest_i.eq(self.dest_i)
- m.d.comb += intregdeps.src1_i.eq(self.src1_i)
- m.d.comb += intregdeps.src2_i.eq(self.src2_i)
+ comb += intregdeps.dest_i.eq(self.dest_i)
+ comb += intregdeps.src1_i.eq(self.src1_i)
+ comb += intregdeps.src2_i.eq(self.src2_i)
- m.d.comb += intregdeps.go_rd_i.eq(self.go_rd_i)
- m.d.comb += intregdeps.go_wr_i.eq(self.go_wr_i)
- m.d.comb += intregdeps.issue_i.eq(self.fn_issue_i)
+ comb += intregdeps.go_rd_i.eq(self.go_rd_i)
+ comb += intregdeps.go_wr_i.eq(self.go_wr_i)
+ comb += intregdeps.issue_i.eq(self.fn_issue_i)
- m.d.comb += self.dest_rsel_o.eq(intregdeps.dest_rsel_o)
- m.d.comb += self.src1_rsel_o.eq(intregdeps.src1_rsel_o)
- m.d.comb += self.src2_rsel_o.eq(intregdeps.src2_rsel_o)
+ comb += self.dest_rsel_o.eq(intregdeps.dest_rsel_o)
+ comb += self.src1_rsel_o.eq(intregdeps.src1_rsel_o)
+ comb += self.src2_rsel_o.eq(intregdeps.src2_rsel_o)
return m
def elaborate(self, platform):
m = Module()
+ comb = m.d.comb
+ sync = m.d.sync
m.submodules.intregs = self.intregs
m.submodules.fpregs = self.fpregs
- # dummy values
- m.d.sync += self.branch_succ_i.eq(Const(0))
- m.d.sync += self.branch_fail_i.eq(Const(0))
- m.d.sync += self.branch_direction_o.eq(Const(0))
-
# register ports
int_dest = self.intregs.write_port("dest")
int_src1 = self.intregs.read_port("src1")
fp_src2 = self.fpregs.read_port("src2")
# Int ALUs and Comp Units
- n_int_alus = 4
+ n_int_alus = 5
m.submodules.cu = cu = CompUnits(self.rwid, n_int_alus)
- m.d.comb += cu.go_die_i.eq(0)
+ comb += cu.go_die_i.eq(0)
+ bgt = cu.bgt # get at the branch computation unit
# Int FUs
m.submodules.intfus = intfus = FunctionUnits(self.n_regs, n_int_alus)
m.submodules.issueunit = issueunit
# Shadow Matrix. currently n_int_fus shadows, to be used for
- # write-after-write hazards
+ # write-after-write hazards. NOTE: there is one extra for branches,
+ # so the shadow width is increased by 1
m.submodules.shadows = shadows = ShadowMatrix(n_int_fus, n_int_fus)
+ m.submodules.bshadow = bshadow = ShadowMatrix(n_int_fus, 1)
+
# combined go_rd/wr + go_die (go_die used to reset latches)
go_rd_rst = Signal(n_int_fus, reset_less=True)
go_wr_rst = Signal(n_int_fus, reset_less=True)
fn_issue_prev = Signal(n_int_fus)
prev_shadow = Signal(n_int_fus)
+ # Branch Speculation recorder. tracks the success/fail state as
+ # each instruction is issued, so that when the branch occurs the
+ # allow/cancel can be issued as appropriate.
+ m.submodules.specrec = bspec = BranchSpeculationRecord(n_int_fus)
+
#---------
# ok start wiring things together...
# "now hear de word of de looord... dem bones dem bones dem dryy bones"
#---------
# Issue Unit is where it starts. set up some in/outs for this module
#---------
- m.d.comb += [issueunit.i.store_i.eq(self.int_store_i),
+ comb += [issueunit.i.store_i.eq(self.int_store_i),
regdecode.dest_i.eq(self.int_dest_i),
regdecode.src1_i.eq(self.int_src1_i),
regdecode.src2_i.eq(self.int_src2_i),
self.int_insn_i = issueunit.i.insn_i # enabled by instruction decode
# connect global rd/wr pending vector (for WaW detection)
- m.d.sync += issueunit.i.g_wr_pend_i.eq(intfus.g_int_wr_pend_o)
+ sync += issueunit.i.g_wr_pend_i.eq(intfus.g_int_wr_pend_o)
# TODO: issueunit.f (FP)
# and int function issue / busy arrays, and dest/src1/src2
- m.d.comb += intfus.dest_i.eq(regdecode.dest_o)
- m.d.comb += intfus.src1_i.eq(regdecode.src1_o)
- m.d.comb += intfus.src2_i.eq(regdecode.src2_o)
+ comb += intfus.dest_i.eq(regdecode.dest_o)
+ comb += intfus.src1_i.eq(regdecode.src1_o)
+ comb += intfus.src2_i.eq(regdecode.src2_o)
fn_issue_o = issueunit.i.fn_issue_o
- m.d.comb += intfus.fn_issue_i.eq(fn_issue_o)
- m.d.comb += issueunit.i.busy_i.eq(cu.busy_o)
- m.d.comb += self.busy_o.eq(cu.busy_o.bool())
+ comb += intfus.fn_issue_i.eq(fn_issue_o)
+ comb += issueunit.i.busy_i.eq(cu.busy_o)
+ comb += self.busy_o.eq(cu.busy_o.bool())
#---------
# connect fu-fu matrix
go_rd_i = intfus.go_rd_i
go_wr_i = intfus.go_wr_i
# NOTE: connect to the shadowed versions so that they can "die" (reset)
- m.d.comb += go_rd_i[0:n_int_fus].eq(go_rd_rst[0:n_int_fus]) # rd
- m.d.comb += go_wr_i[0:n_int_fus].eq(go_wr_rst[0:n_int_fus]) # wr
+ comb += go_rd_i[0:n_int_fus].eq(go_rd_rst[0:n_int_fus]) # rd
+ comb += go_wr_i[0:n_int_fus].eq(go_wr_rst[0:n_int_fus]) # wr
# Connect Picker
#---------
- m.d.comb += intpick1.rd_rel_i[0:n_int_fus].eq(cu.rd_rel_o[0:n_int_fus])
- m.d.comb += intpick1.req_rel_i[0:n_int_fus].eq(cu.req_rel_o[0:n_int_fus])
+ comb += intpick1.rd_rel_i[0:n_int_fus].eq(cu.rd_rel_o[0:n_int_fus])
+ comb += intpick1.req_rel_i[0:n_int_fus].eq(cu.req_rel_o[0:n_int_fus])
int_rd_o = intfus.readable_o
int_wr_o = intfus.writable_o
- m.d.comb += intpick1.readable_i[0:n_int_fus].eq(int_rd_o[0:n_int_fus])
- m.d.comb += intpick1.writable_i[0:n_int_fus].eq(int_wr_o[0:n_int_fus])
+ comb += intpick1.readable_i[0:n_int_fus].eq(int_rd_o[0:n_int_fus])
+ comb += intpick1.writable_i[0:n_int_fus].eq(int_wr_o[0:n_int_fus])
#---------
# Shadow Matrix
#---------
- m.d.comb += shadows.issue_i.eq(fn_issue_o)
+ comb += shadows.issue_i.eq(fn_issue_o)
# these are explained in ShadowMatrix docstring, and are to be
# connected to the FUReg and FUFU Matrices, to get them to reset
# NOTE: do NOT connect these to the Computation Units. The CUs need to
# do something slightly different (due to the revolving-door SRLatches)
- m.d.comb += go_rd_rst.eq(go_rd_o | shadows.go_die_o)
- m.d.comb += go_wr_rst.eq(go_wr_o | shadows.go_die_o)
+ anydie = Signal(n_int_fus, reset_less=True)
+ allshadown = Signal(n_int_fus, reset_less=True)
+ comb += allshadown.eq(shadows.shadown_o & bshadow.shadown_o)
+ comb += anydie.eq(shadows.go_die_o | bshadow.go_die_o)
+ comb += go_rd_rst.eq(go_rd_o | anydie)
+ comb += go_wr_rst.eq(go_wr_o | anydie)
+
+ #---------
+ # NOTE; this setup is for the instruction order preservation...
# connect shadows / go_dies to Computation Units
- m.d.comb += cu.shadown_i[0:n_int_fus].eq(shadows.shadown_o[0:n_int_fus])
- m.d.comb += cu.go_die_i[0:n_int_fus].eq(shadows.go_die_o[0:n_int_fus])
+ comb += cu.shadown_i[0:n_int_fus].eq(allshadown)
+ comb += cu.go_die_i[0:n_int_fus].eq(anydie)
# ok connect first n_int_fu shadows to busy lines, to create an
# instruction-order linked-list-like arrangement, using a bit-matrix
# XXX TODO
# when written, the shadow can be cancelled (and was good)
- m.d.comb += shadows.s_good_i[0:n_int_fus].eq(go_wr_o[0:n_int_fus])
+ for i in range(n_int_fus):
+ comb += shadows.s_good_i[i][0:n_int_fus].eq(go_wr_o[0:n_int_fus])
# work out the current-activated busy unit (by recording the old one)
with m.If(fn_issue_o): # only update prev bit if instruction issued
- m.d.sync += fn_issue_prev.eq(fn_issue_o)
+ sync += fn_issue_prev.eq(fn_issue_o)
# *previous* instruction shadows *current* instruction, and, obviously,
# if the previous is completed (!busy) don't cast the shadow!
- m.d.comb += prev_shadow.eq(~fn_issue_o & fn_issue_prev & cu.busy_o)
+ comb += prev_shadow.eq(~fn_issue_o & fn_issue_prev & cu.busy_o)
for i in range(n_int_fus):
- m.d.comb += shadows.shadow_i[i].eq(prev_shadow)
+ comb += shadows.shadow_i[i][0:n_int_fus].eq(prev_shadow)
+
+ #---------
+ # ... and this is for branch speculation. it uses the extra bit
+ # tacked onto the ShadowMatrix (hence shadow_wid=n_int_fus+1)
+ # only needs to set shadow_i, s_fail_i and s_good_i
+
+ # issue captures shadow_i (if enabled)
+ comb += bshadow.issue_i.eq(fn_issue_o)
+
+ # instruction being issued (fn_issue_o) has a shadow cast by the branch
+ with m.If(self.branch_succ_i | self.branch_fail_i):
+ comb += bshadow.shadow_i[fn_issue_o][0].eq(1)
+
+ # finally, we need an indicator to the test infrastructure as to
+ # whether the branch succeeded or failed, plus, link up to the
+ # "recorder" of whether the instruction was under shadow or not
+
+ with m.If(cu.br1.issue_i):
+ sync += bspec.active_i.eq(1)
+ with m.If(self.branch_succ_i):
+ comb += bspec.good_i.eq(fn_issue_o & 0xf)
+ with m.If(self.branch_fail_i):
+ comb += bspec.fail_i.eq(fn_issue_o & 0xf)
+
+ # branch is active (TODO: a better signal: this is over-using the
+ # go_write signal - actually the branch should not be "writing")
+ with m.If(cu.br1.go_wr_i):
+ sync += self.branch_direction_o.eq(cu.br1.data_o+Const(1, 2))
+ sync += bspec.active_i.eq(0)
+ comb += bspec.br_i.eq(1)
+ # branch occurs if data == 1, failed if data == 0
+ comb += bspec.br_ok_i.eq(cu.br1.data_o == 1)
+ for i in range(n_int_fus):
+ # *expected* direction of the branch matched against *actual*
+ comb += bshadow.s_good_i[i][0].eq(bspec.match_g_o[i])
+ # ... or it didn't
+ comb += bshadow.s_fail_i[i][0].eq(bspec.match_f_o[i])
#---------
# Connect Register File(s)
#---------
print ("intregdeps wen len", len(intfus.dest_rsel_o))
- m.d.comb += int_dest.wen.eq(intfus.dest_rsel_o)
- m.d.comb += int_src1.ren.eq(intfus.src1_rsel_o)
- m.d.comb += int_src2.ren.eq(intfus.src2_rsel_o)
+ comb += int_dest.wen.eq(intfus.dest_rsel_o)
+ comb += int_src1.ren.eq(intfus.src1_rsel_o)
+ comb += int_src2.ren.eq(intfus.src2_rsel_o)
# connect ALUs to regfule
- m.d.comb += int_dest.data_i.eq(cu.dest_o)
- m.d.comb += cu.src1_data_i.eq(int_src1.data_o)
- m.d.comb += cu.src2_data_i.eq(int_src2.data_o)
+ comb += int_dest.data_i.eq(cu.dest_o)
+ comb += cu.src1_data_i.eq(int_src1.data_o)
+ comb += cu.src2_data_i.eq(int_src2.data_o)
# connect ALU Computation Units
- m.d.comb += cu.go_rd_i[0:n_int_fus].eq(go_rd_o[0:n_int_fus])
- m.d.comb += cu.go_wr_i[0:n_int_fus].eq(go_wr_o[0:n_int_fus])
- m.d.comb += cu.issue_i[0:n_int_fus].eq(fn_issue_o[0:n_int_fus])
+ comb += cu.go_rd_i[0:n_int_fus].eq(go_rd_o[0:n_int_fus])
+ comb += cu.go_wr_i[0:n_int_fus].eq(go_wr_o[0:n_int_fus])
+ comb += cu.issue_i[0:n_int_fus].eq(fn_issue_o[0:n_int_fus])
return m
ISUB = 1
IMUL = 2
ISHF = 3
-IBGE = 4
+IBGT = 4
IBLT = 5
IBEQ = 6
IBNE = 7
def op(self, op, src1, src2, dest):
maxbits = (1 << self.rwidth) - 1
- src1 = self.regs[src1]
- src2 = self.regs[src2]
+ src1 = self.regs[src1] & maxbits
+ src2 = self.regs[src2] & maxbits
if op == IADD:
val = src1 + src2
elif op == ISUB:
val = src1 * src2
elif op == ISHF:
val = src1 >> (src2 & maxbits)
- elif op == IBGE:
+ elif op == IBGT:
val = int(src1 > src2)
elif op == IBLT:
val = int(src1 < src2)
print ("reg %s: %s" % (','.join(rnums), ','.join(rs)))
-def create_random_ops(n_ops, shadowing=False):
+def create_random_ops(dut, n_ops, shadowing=False, max_opnums=3):
insts = []
for i in range(n_ops):
src1 = randint(1, dut.n_regs-1)
src2 = randint(1, dut.n_regs-1)
dest = randint(1, dut.n_regs-1)
- op = randint(0, 3)
+ op = randint(0, max_opnums)
if shadowing:
- instrs.append((src1, src2, dest, op, (False, False)))
+ insts.append((src1, src2, dest, op, (0, 0)))
else:
- instrs.append((src1, src2, dest, op))
+ insts.append((src1, src2, dest, op))
return insts
def scoreboard_branch_sim(dut, alusim):
+ seed(0)
+
yield dut.int_store_i.eq(1)
for i in range(2):
alusim.setval(i, val)
# create some instructions: branches create a tree
- insts = create_random_ops(5)
+ insts = create_random_ops(dut, 1, True)
src1 = randint(1, dut.n_regs-1)
src2 = randint(1, dut.n_regs-1)
- op = randint(4, 7)
+ #op = randint(4, 7)
+ op = 4 # only BGT at the moment
- branch_ok = create_random_ops(5)
- branch_fail = create_random_ops(5)
+ branch_ok = create_random_ops(dut, 1, True)
+ branch_fail = create_random_ops(dut, 1, True)
insts.append((src1, src2, (branch_ok, branch_fail), op, (0, 0)))
is_branch = op >= 4
if is_branch:
branch_ok, branch_fail = dest
- dest = None
+ dest = -1
# ok zip up the branch success / fail instructions and
# drop them into the queue, one marked "to have branch success"
# the other to be marked shadow branch "fail".
shadow_on, shadow_off)
yield
yield from wait_for_issue(dut)
- branch_direction = dut.branch_direction_o # which way branch went
+ branch_direction = yield dut.branch_direction_o # way branch went
# wait for all instructions to stop before checking
yield
yield dut.int_store_i.eq(1)
- for i in range(2):
+ for i in range(1):
# set random values in the registers
for i in range(1, dut.n_regs):
# create some instructions (some random, some regression tests)
instrs = []
if True:
- for i in range(10):
- src1 = randint(1, dut.n_regs-1)
- src2 = randint(1, dut.n_regs-1)
- while True:
- dest = randint(1, dut.n_regs-1)
- break
- if dest not in [src1, src2]:
- break
- #src1 = 2
- #src2 = 3
- #dest = 2
-
- op = randint(0, 3)
- #op = i % 2
- #op = 0
-
- instrs.append((src1, src2, dest, op))
+ instrs = create_random_ops(dut, 10, True, 4)
if False:
instrs.append((2, 3, 3, 0))
instrs.append( (2, 6, 3, 0) )
instrs.append( (4, 2, 2, 1) )
+ if False:
+ v1 = 4
+ yield dut.intregs.regs[5].reg.eq(v1)
+ alusim.setval(5, v1)
+ yield dut.intregs.regs[3].reg.eq(5)
+ alusim.setval(3, 5)
+ instrs.append((5, 3, 3, 4, (0, 0)))
+ instrs.append((4, 2, 1, 2, (0, 1)))
+
+ if False:
+ v1 = 6
+ yield dut.intregs.regs[5].reg.eq(v1)
+ alusim.setval(5, v1)
+ yield dut.intregs.regs[3].reg.eq(5)
+ alusim.setval(3, 5)
+ instrs.append((5, 3, 3, 4, (0, 0)))
+ instrs.append((4, 2, 1, 2, (1, 0)))
+
# issue instruction(s), wait for issue to be free before proceeding
- for i, (src1, src2, dest, op) in enumerate(instrs):
+ for i, (src1, src2, dest, op, (br_ok, br_fail)) in enumerate(instrs):
print ("instr %d: (%d, %d, %d, %d)" % (i, src1, src2, dest, op))
alusim.op(op, src1, src2, dest)
- yield from int_instr(dut, op, src1, src2, dest, 0, 0)
+ yield from int_instr(dut, op, src1, src2, dest, br_ok, br_fail)
yield
yield from wait_for_issue(dut)
yield from alusim.dump(dut)
-def explore_groups(dut):
- from nmigen.hdl.ir import Fragment
- from nmigen.hdl.xfrm import LHSGroupAnalyzer
-
- fragment = dut.elaborate(platform=None)
- fr = Fragment.get(fragment, platform=None)
-
- groups = LHSGroupAnalyzer()(fragment._statements)
-
- print (groups)
-
-
def test_scoreboard():
dut = Scoreboard(16, 8)
alusim = RegSim(16, 8)
with open("test_scoreboard6600.il", "w") as f:
f.write(vl)
- run_simulation(dut, scoreboard_sim(dut, alusim),
+ #run_simulation(dut, scoreboard_sim(dut, alusim),
+ # vcd_name='test_scoreboard6600.vcd')
+
+ run_simulation(dut, scoreboard_branch_sim(dut, alusim),
vcd_name='test_scoreboard6600.vcd')
projects / soc.git / blobdiff