rewrote the logic in div[02].py; fdiv/fsqrt/frsqrt all works!

[ieee754fpu.git] / src / ieee754 / div_rem_sqrt_rsqrt / div_pipe.py

diff --git a/src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py b/src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py
index 438fc619711b385fef66fe5aa14021ca5ed871c0..f1b440a1392dca8d101a195e56eb5f972218af34 100644 (file)
--- a/src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py
+++ b/src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py
@@ -10,7 +10,7 @@ from ieee754.div_rem_sqrt_rsqrt.core import (DivPipeCoreConfig,
                                              DivPipeCoreSetupStage,
                                              DivPipeCoreCalculateStage,
                                              DivPipeCoreFinalStage,
-                                            )
+                                             )
 from ieee754.fpcommon.getop import FPPipeContext
 from ieee754.fpcommon.fpbase import FPFormat, FPNumBaseRecord
 
@@ -34,7 +34,8 @@ class DivPipeBaseData:
         """ Create a ``DivPipeBaseData`` instance. """
         self.pspec = pspec
         width = pspec.width
-        self.z = FPNumBaseRecord(width, False) # s and e carried: m ignored
+        # s and e carried: m ignored
+        self.z = FPNumBaseRecord(width, False, name="z")
         self.out_do_z = Signal(reset_less=True)
         self.oz = Signal(width, reset_less=True)
 
@@ -71,7 +72,7 @@ class DivPipeInputData(DivPipeCoreInputData, DivPipeBaseData):
     def eq(self, rhs):
         """ Assign member signals. """
         return DivPipeCoreInputData.eq(self, rhs) + \
-               DivPipeBaseData.eq(self, rhs)
+            DivPipeBaseData.eq(self, rhs)
 
 
 class DivPipeInterstageData(DivPipeCoreInterstageData, DivPipeBaseData):
@@ -91,7 +92,7 @@ class DivPipeInterstageData(DivPipeCoreInterstageData, DivPipeBaseData):
         """ Assign member signals. """
         #print (self, rhs)
         return DivPipeCoreInterstageData.eq(self, rhs) + \
-               DivPipeBaseData.eq(self, rhs)
+            DivPipeBaseData.eq(self, rhs)
 
 
 class DivPipeOutputData(DivPipeCoreOutputData, DivPipeBaseData):
@@ -110,7 +111,7 @@ class DivPipeOutputData(DivPipeCoreOutputData, DivPipeBaseData):
     def eq(self, rhs):
         """ Assign member signals. """
         return DivPipeCoreOutputData.eq(self, rhs) + \
-               DivPipeBaseData.eq(self, rhs)
+            DivPipeBaseData.eq(self, rhs)
 
 
 class DivPipeBaseStage:
@@ -124,6 +125,7 @@ class DivPipeBaseStage:
 
 
 class DivPipeSetupStage(DivPipeBaseStage, DivPipeCoreSetupStage):
+    """ FIXME: add docs. """
 
     def __init__(self, pspec):
         self.pspec = pspec
@@ -146,10 +148,12 @@ class DivPipeSetupStage(DivPipeBaseStage, DivPipeCoreSetupStage):
 
 
 class DivPipeCalculateStage(DivPipeBaseStage, DivPipeCoreCalculateStage):
+    """ FIXME: add docs. """
 
     def __init__(self, pspec, stage_index):
         self.pspec = pspec
-        DivPipeCoreCalculateStage.__init__(self, pspec.core_config, stage_index)
+        DivPipeCoreCalculateStage.__init__(
+            self, pspec.core_config, stage_index)
 
     def ispec(self):
         """ Get the input spec for this pipeline stage."""
@@ -167,6 +171,7 @@ class DivPipeCalculateStage(DivPipeBaseStage, DivPipeCoreCalculateStage):
 
 
 class DivPipeFinalStage(DivPipeBaseStage, DivPipeCoreFinalStage):
+    """ FIXME: add docs. """
 
     def __init__(self, pspec):
         self.pspec = pspec
@@ -185,4 +190,3 @@ class DivPipeFinalStage(DivPipeBaseStage, DivPipeCoreFinalStage):
         m = DivPipeCoreFinalStage.elaborate(self, platform)
         self._elaborate(m, platform)
         return m
-