fix imports

[ieee754fpu.git] / src / ieee754 / div_rem_sqrt_rsqrt / div_pipe.py

diff --git a/src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py b/src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py
index 7daac8a9824edb0592599d0fe7bd8ed59b07e68d..353ccc4fc7594f91cfbf90000cfc8ad3ced04f59 100644 (file)
--- a/src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py
+++ b/src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py
@@ -2,23 +2,30 @@
 # See Notices.txt for copyright information
 """ div/rem/sqrt/rsqrt pipeline. """
 
-from .core import (DivPipeCoreConfig, DivPipeCoreInputData,
-                   DivPipeCoreInterstageData, DivPipeCoreOutputData)
+from ieee754.div_rem_sqrt_rsqrt.core import (DivPipeCoreConfig,
+                                             DivPipeCoreInputData,
+                                             DivPipeCoreInterstageData,
+                                             DivPipeCoreOutputData,
+                                             DivPipeCoreSetupStage,
+                                             DivPipeCoreCalculateStage,
+                                             DivPipeCoreFinalStage,
+                                            )
 from ieee754.fpcommon.getop import FPPipeContext
+from ieee754.fpcommon.fpbase import FPFormat, FPNumBaseRecord
 
 
 class DivPipeConfig:
     """ Configuration for the div/rem/sqrt/rsqrt pipeline.
 
-    :attribute pspec: FIXME: document
+    :attribute pspec: ``PipelineSpec`` instance
     :attribute core_config: the ``DivPipeCoreConfig`` instance.
     """
 
-    def __init__(self, pspec):
+    def __init__(self, pspec, log2_radix=3):
         """ Create a ``DivPipeConfig`` instance. """
         self.pspec = pspec
-        # FIXME: get bit_width, fract_width, and log2_radix from pspec or pass
-        # in as arguments
+        bit_width = pspec.width
+        fract_width = FPFormat.standard(bit_width).fraction_width
         self.core_config = DivPipeCoreConfig(bit_width,
                                              fract_width,
                                              log2_radix)
@@ -27,6 +34,9 @@ class DivPipeConfig:
 class DivPipeBaseData:
     """ input data base type for ``DivPipe``.
 
+    :attribute z: a convenient way to carry the sign and exponent through
+                  the pipeline from when they were computed right at the
+                  start.
     :attribute out_do_z: FIXME: document
     :attribute oz: FIXME: document
     :attribute ctx: FIXME: document
@@ -40,6 +50,7 @@ class DivPipeBaseData:
         """ Create a ``DivPipeBaseData`` instance. """
         self.config = config
         width = config.pspec.width
+        self.z = FPNumBaseRecord(width, False) # s and e carried: m ignored
         self.out_do_z = Signal(reset_less=True)
         self.oz = Signal(width, reset_less=True)
 
@@ -49,13 +60,14 @@ class DivPipeBaseData:
 
     def __iter__(self):
         """ Get member signals. """
+        yield from self.z
         yield self.out_do_z
         yield self.oz
         yield from self.ctx
 
     def eq(self, rhs):
         """ Assign member signals. """
-        return [self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
+        return [self.z.eq(rhs.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
                 self.ctx.eq(i.ctx)]
 
 
@@ -120,15 +132,50 @@ class DivPipeBaseStage:
     """ Base Mix-in for DivPipe*Stage. """
 
     def _elaborate(self, m, platform):
+        m.d.comb += self.o.z.eq(self.i.z)
         m.d.comb += self.o.oz.eq(self.i.oz)
         m.d.comb += self.o.out_do_z.eq(self.i.out_do_z)
         m.d.comb += self.o.ctx.eq(self.i.ctx)
 
-# FIXME: in DivPipeSetupStage.elaborate
-# DivPipeBaseStage._elaborate(self, m, platform)
+    def get_core_config(self):
+        m_width = self.pspec.m_width # mantissa width
+        # 4 extra bits on the mantissa: MSB is zero, MSB-1 is 1
+        # then there is guard and round at the LSB end
+        return DivPipeCoreConfig(m_width+4, 0, log_radix=2)
+
+
+class DivPipeSetupStage(DivPipeBaseStage, DivPipeCoreSetupStage):
+
+    def __init__(self, pspec):
+        DivPipeCoreSetupStage.__init__(self.get_core_config())
+        self.pspec = pspec
+
+    def elaborate(self, platform):
+        m = DivPipeCoreSetupStage(platform) # XXX TODO: out_do_z logic!
+        self._elaborate(m, platform)
+        return m
+
+
+class DivPipeCalculateStage(DivPipeBaseStage, DivPipeCoreCalculateStage):
+
+    def __init__(self, pspec, stage_index):
+        DivPipeCoreCalculateStage.__init__(self.get_core_config(), stage_index)
+        self.pspec = pspec
+
+    def elaborate(self, platform):
+        m = DivPipeCoreCalculateStage(platform) # XXX TODO: out_do_z logic!
+        self._elaborate(m, platform)
+        return m
+
+
+class DivPipeFinalStage(DivPipeBaseStage, DivPipeCoreFinalStage):
+
+    def __init__(self, pspec, stage_index):
+        DivPipeCoreFinalStage.__init__(self.get_core_config(), stage_index)
+        self.pspec = pspec
 
-# FIXME: in DivPipeCalculateStage.elaborate
-# DivPipeBaseStage._elaborate(self, m, platform)
+    def elaborate(self, platform):
+        m = DivPipeCoreCalculateStage(platform) # XXX TODO: out_do_z logic!
+        self._elaborate(m, platform)
+        return m
 
-# FIXME: in DivPipeFinalStage.elaborate
-# DivPipeBaseStage._elaborate(self, m, platform)