DivPipeCoreSetupStage,
DivPipeCoreCalculateStage,
DivPipeCoreFinalStage,
- )
+ )
from ieee754.fpcommon.getop import FPPipeContext
from ieee754.fpcommon.fpbase import FPFormat, FPNumBaseRecord
""" Create a ``DivPipeBaseData`` instance. """
self.pspec = pspec
width = pspec.width
- self.z = FPNumBaseRecord(width, False) # s and e carried: m ignored
+ # s and e carried: m ignored
+ self.z = FPNumBaseRecord(width, False, name="z")
self.out_do_z = Signal(reset_less=True)
self.oz = Signal(width, reset_less=True)
def eq(self, rhs):
""" Assign member signals. """
return DivPipeCoreInputData.eq(self, rhs) + \
- DivPipeBaseData.eq(self, rhs)
+ DivPipeBaseData.eq(self, rhs)
class DivPipeInterstageData(DivPipeCoreInterstageData, DivPipeBaseData):
def eq(self, rhs):
""" Assign member signals. """
- print (self, rhs)
+ #print (self, rhs)
return DivPipeCoreInterstageData.eq(self, rhs) + \
- DivPipeBaseData.eq(self, rhs)
+ DivPipeBaseData.eq(self, rhs)
class DivPipeOutputData(DivPipeCoreOutputData, DivPipeBaseData):
def eq(self, rhs):
""" Assign member signals. """
return DivPipeCoreOutputData.eq(self, rhs) + \
- DivPipeBaseData.eq(self, rhs)
+ DivPipeBaseData.eq(self, rhs)
class DivPipeBaseStage:
""" Base Mix-in for DivPipe*Stage. """
def _elaborate(self, m, platform):
+ m.d.comb += self.o.ctx.eq(self.i.ctx)
m.d.comb += self.o.z.eq(self.i.z)
m.d.comb += self.o.oz.eq(self.i.oz)
m.d.comb += self.o.out_do_z.eq(self.i.out_do_z)
- m.d.comb += self.o.ctx.eq(self.i.ctx)
-
- def get_core_config(self):
- m_width = self.pspec.m_width # mantissa width
- # 4 extra bits on the mantissa: MSB is zero, MSB-1 is 1
- # then there is guard and round at the LSB end
- return DivPipeCoreConfig(m_width+4, 0, log_radix=2)
class DivPipeSetupStage(DivPipeBaseStage, DivPipeCoreSetupStage):
+ """ FIXME: add docs. """
def __init__(self, pspec):
self.pspec = pspec
+ #print ("DivPipeSetupStage", pspec, pspec.core_config)
DivPipeCoreSetupStage.__init__(self, pspec.core_config)
+ def ispec(self):
+ """ Get the input spec for this pipeline stage."""
+ return DivPipeInputData(self.pspec)
+
+ def ospec(self):
+ """ Get the output spec for this pipeline stage."""
+ return DivPipeInterstageData(self.pspec)
+
def elaborate(self, platform):
- m = DivPipeCoreSetupStage(platform) # XXX TODO: out_do_z logic!
+ # XXX TODO: out_do_z logic!
+ m = DivPipeCoreSetupStage.elaborate(self, platform)
self._elaborate(m, platform)
return m
class DivPipeCalculateStage(DivPipeBaseStage, DivPipeCoreCalculateStage):
+ """ FIXME: add docs. """
- def __init__(self, pspec, stage_index):
+ def __init__(self, pspec, stage_idx):
self.pspec = pspec
- DivPipeCoreCalculateStage.__init__(self, pspec.core_config, stage_index)
+ DivPipeCoreCalculateStage.__init__(self, pspec.core_config, stage_idx)
+
+ def ispec(self):
+ """ Get the input spec for this pipeline stage."""
+ return DivPipeInterstageData(self.pspec)
+
+ def ospec(self):
+ """ Get the output spec for this pipeline stage."""
+ return DivPipeInterstageData(self.pspec)
def elaborate(self, platform):
- m = DivPipeCoreCalculateStage(platform) # XXX TODO: out_do_z logic!
+ # XXX TODO: out_do_z logic!
+ m = DivPipeCoreCalculateStage.elaborate(self, platform)
self._elaborate(m, platform)
return m
class DivPipeFinalStage(DivPipeBaseStage, DivPipeCoreFinalStage):
+ """ FIXME: add docs. """
- def __init__(self, pspec, stage_index):
+ def __init__(self, pspec):
self.pspec = pspec
- DivPipeCoreFinalStage.__init__(self, pspec.core_config, stage_index)
+ DivPipeCoreFinalStage.__init__(self, pspec.core_config)
+
+ def ispec(self):
+ """ Get the input spec for this pipeline stage."""
+ return DivPipeInterstageData(self.pspec)
+
+ def ospec(self):
+ """ Get the output spec for this pipeline stage."""
+ return DivPipeOutputData(self.pspec)
def elaborate(self, platform):
- m = DivPipeCoreCalculateStage(platform) # XXX TODO: out_do_z logic!
+ # XXX TODO: out_do_z logic!
+ m = DivPipeCoreFinalStage.elaborate(self, platform)
self._elaborate(m, platform)
return m
-