fix tests/mark as expected failure

[ieee754fpu.git] / src / ieee754 / div_rem_sqrt_rsqrt / div_pipe.py

diff --git a/src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py b/src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py
index 2facb95aa9b8beb1fc3f80155abd465f590d6287..d7b81729499b5d763eb1d150b031dceeefecbda9 100644 (file)
--- a/src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py
+++ b/src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py
@@ -10,7 +10,7 @@ from ieee754.div_rem_sqrt_rsqrt.core import (DivPipeCoreConfig,
                                              DivPipeCoreSetupStage,
                                              DivPipeCoreCalculateStage,
                                              DivPipeCoreFinalStage,
-                                            )
+                                             )
 from ieee754.fpcommon.getop import FPPipeContext
 from ieee754.fpcommon.fpbase import FPFormat, FPNumBaseRecord
 
@@ -34,7 +34,8 @@ class DivPipeBaseData:
         """ Create a ``DivPipeBaseData`` instance. """
         self.pspec = pspec
         width = pspec.width
-        self.z = FPNumBaseRecord(width, False) # s and e carried: m ignored
+        # s and e carried: m ignored
+        self.z = FPNumBaseRecord(width, False, name="z")
         self.out_do_z = Signal(reset_less=True)
         self.oz = Signal(width, reset_less=True)
 
@@ -71,7 +72,7 @@ class DivPipeInputData(DivPipeCoreInputData, DivPipeBaseData):
     def eq(self, rhs):
         """ Assign member signals. """
         return DivPipeCoreInputData.eq(self, rhs) + \
-            DivPipeBaseData.eq(self, rhs)
+               DivPipeBaseData.eq(self, rhs)
 
 
 class DivPipeInterstageData(DivPipeCoreInterstageData, DivPipeBaseData):
@@ -89,8 +90,9 @@ class DivPipeInterstageData(DivPipeCoreInterstageData, DivPipeBaseData):
 
     def eq(self, rhs):
         """ Assign member signals. """
+        #print (self, rhs)
         return DivPipeCoreInterstageData.eq(self, rhs) + \
-            DivPipeBaseData.eq(self, rhs)
+               DivPipeBaseData.eq(self, rhs)
 
 
 class DivPipeOutputData(DivPipeCoreOutputData, DivPipeBaseData):
@@ -109,57 +111,81 @@ class DivPipeOutputData(DivPipeCoreOutputData, DivPipeBaseData):
     def eq(self, rhs):
         """ Assign member signals. """
         return DivPipeCoreOutputData.eq(self, rhs) + \
-            DivPipeBaseData.eq(self, rhs)
+               DivPipeBaseData.eq(self, rhs)
 
 
 class DivPipeBaseStage:
     """ Base Mix-in for DivPipe*Stage. """
 
     def _elaborate(self, m, platform):
+        m.d.comb += self.o.ctx.eq(self.i.ctx)
         m.d.comb += self.o.z.eq(self.i.z)
         m.d.comb += self.o.oz.eq(self.i.oz)
         m.d.comb += self.o.out_do_z.eq(self.i.out_do_z)
-        m.d.comb += self.o.ctx.eq(self.i.ctx)
-
-    def get_core_config(self):
-        m_width = self.pspec.m_width # mantissa width
-        # 4 extra bits on the mantissa: MSB is zero, MSB-1 is 1
-        # then there is guard and round at the LSB end
-        return DivPipeCoreConfig(m_width+4, 0, log_radix=2)
 
 
 class DivPipeSetupStage(DivPipeBaseStage, DivPipeCoreSetupStage):
+    """ FIXME: add docs. """
 
     def __init__(self, pspec):
-        DivPipeCoreSetupStage.__init__(self.get_core_config())
         self.pspec = pspec
+        #print ("DivPipeSetupStage", pspec, pspec.core_config)
+        DivPipeCoreSetupStage.__init__(self, pspec.core_config)
+
+    def ispec(self):
+        """ Get the input spec for this pipeline stage."""
+        return DivPipeInputData(self.pspec)
+
+    def ospec(self):
+        """ Get the output spec for this pipeline stage."""
+        return DivPipeInterstageData(self.pspec)
 
     def elaborate(self, platform):
-        m = DivPipeCoreSetupStage(platform) # XXX TODO: out_do_z logic!
+        # XXX TODO: out_do_z logic!
+        m = DivPipeCoreSetupStage.elaborate(self, platform)
         self._elaborate(m, platform)
         return m
 
 
 class DivPipeCalculateStage(DivPipeBaseStage, DivPipeCoreCalculateStage):
+    """ FIXME: add docs. """
 
-    def __init__(self, pspec, stage_index):
-        DivPipeCoreCalculateStage.__init__(self.get_core_config(), stage_index)
+    def __init__(self, pspec, stage_idx):
         self.pspec = pspec
+        DivPipeCoreCalculateStage.__init__(self, pspec.core_config, stage_idx)
+
+    def ispec(self):
+        """ Get the input spec for this pipeline stage."""
+        return DivPipeInterstageData(self.pspec)
+
+    def ospec(self):
+        """ Get the output spec for this pipeline stage."""
+        return DivPipeInterstageData(self.pspec)
 
     def elaborate(self, platform):
-        m = DivPipeCoreCalculateStage(platform) # XXX TODO: out_do_z logic!
+        # XXX TODO: out_do_z logic!
+        m = DivPipeCoreCalculateStage.elaborate(self, platform)
         self._elaborate(m, platform)
         return m
 
 
 class DivPipeFinalStage(DivPipeBaseStage, DivPipeCoreFinalStage):
+    """ FIXME: add docs. """
 
-    def __init__(self, pspec, stage_index):
-        DivPipeCoreFinalStage.__init__(self.get_core_config(), stage_index)
+    def __init__(self, pspec):
         self.pspec = pspec
+        DivPipeCoreFinalStage.__init__(self, pspec.core_config)
+
+    def ispec(self):
+        """ Get the input spec for this pipeline stage."""
+        return DivPipeInterstageData(self.pspec)
+
+    def ospec(self):
+        """ Get the output spec for this pipeline stage."""
+        return DivPipeOutputData(self.pspec)
 
     def elaborate(self, platform):
-        m = DivPipeCoreCalculateStage(platform) # XXX TODO: out_do_z logic!
+        # XXX TODO: out_do_z logic!
+        m = DivPipeCoreFinalStage.elaborate(self, platform)
         self._elaborate(m, platform)
         return m
-