remove "fail" in test

[ieee754fpu.git] / src / ieee754 / div_rem_sqrt_rsqrt / test_core.py

diff --git a/src/ieee754/div_rem_sqrt_rsqrt/test_core.py b/src/ieee754/div_rem_sqrt_rsqrt/test_core.py
index 6a174ce2c150f78e2263bcb85635f060f1d650b7..3d58d0debdb493be0c88c93fb3b80ddca0afbf82 100644 (file)
--- a/src/ieee754/div_rem_sqrt_rsqrt/test_core.py
+++ b/src/ieee754/div_rem_sqrt_rsqrt/test_core.py
@@ -186,7 +186,6 @@ class TestDivPipeCore(unittest.TestCase):
             vl = rtlil.convert(dut, ports=[*dut.i, *dut.o])
             with open(f"{base_name}.il", "w") as f:
                 f.write(vl)
-        self.fail("generated invalid rtlil")  # FIXME: remove when fixed
         dut = DivPipeCoreTestPipeline(core_config)
         with Simulator(dut,
                        vcd_file=f"{base_name}.vcd",