split out adder code (PartitionedAdder) into module, PartitionPoints too

[ieee754fpu.git] / src / ieee754 / fclass / fclass.py

diff --git a/src/ieee754/fclass/fclass.py b/src/ieee754/fclass/fclass.py
index 3bad5c24cfb2067a578904bdcd5ed17c42472510..8d5de09ecfb3147844c90255ab046b2ecbaea93c 100644 (file)
--- a/src/ieee754/fclass/fclass.py
+++ b/src/ieee754/fclass/fclass.py
@@ -3,13 +3,13 @@
 
 from nmigen import Module, Signal, Cat
 
-from ieee754.fpcommon.modbase import FPModBase
-from ieee754.fpcommon.getop import FPADDBaseData
+from nmutil.pipemodbase import PipeModBase
+from ieee754.fpcommon.basedata import FPBaseData
 from ieee754.fpcommon.pack import FPPackData
 from ieee754.fpcommon.fpbase import FPNumDecode, FPNumBaseRecord
 
 
-class FPClassMod(FPModBase):
+class FPClassMod(PipeModBase):
     """ obtains floating point information (zero, nan, inf etc.)
     """
     def __init__(self, in_pspec, out_pspec):
@@ -18,7 +18,7 @@ class FPClassMod(FPModBase):
         super().__init__(in_pspec, "fclass")
 
     def ispec(self):
-        return FPADDBaseData(self.in_pspec)
+        return FPBaseData(self.in_pspec)
 
     def ospec(self):
         return FPPackData(self.out_pspec)