add f32/f64 fclass

[ieee754fpu.git] / src / ieee754 / fclass / pipeline.py

diff --git a/src/ieee754/fclass/pipeline.py b/src/ieee754/fclass/pipeline.py
index 6a3ddb381c145a7f9858afcca9b21ab7a236f4f7..6550e684feca2e8daaba8bc43e32e8f89e871d06 100644 (file)
--- a/src/ieee754/fclass/pipeline.py
+++ b/src/ieee754/fclass/pipeline.py
@@ -52,7 +52,7 @@ class FPClassMod(Elaboratable):
     def setup(self, m, i):
         """ links module to inputs and outputs
         """
-        m.submodules.upconvert = self
+        m.submodules.fclass = self
         m.d.comb += self.i.eq(i)
 
     def process(self, i):
@@ -116,7 +116,7 @@ class FPClassBasePipe(ControlBase):
 
     def elaborate(self, platform):
         m = ControlBase.elaborate(self, platform)
-        m.submodules.down = self.pipe1
+        m.submodules.fclass = self.pipe1
         m.d.comb += self._eqs
         return m