add comment about simulation bugs

[ieee754fpu.git] / src / ieee754 / fcvt / pipeline.py

diff --git a/src/ieee754/fcvt/pipeline.py b/src/ieee754/fcvt/pipeline.py
index 4f0e0e9c17d1e5f45d529074294065c73a79e0aa..5e6cc19dee7f98c971d1ea7e2266339b4bf4d2ec 100644 (file)
--- a/src/ieee754/fcvt/pipeline.py
+++ b/src/ieee754/fcvt/pipeline.py
@@ -1,26 +1,16 @@
-# IEEE754 Floating Point Conversion
-# Copyright (C) 2019 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+"""IEEE754 Floating Point Conversion
 
+Copyright (C) 2019 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+
+"""
 
 import sys
 import functools
 
-from nmigen import Module, Signal, Cat, Const, Mux, Elaboratable
-from nmigen.cli import main, verilog
-
 from nmutil.singlepipe import ControlBase
 from nmutil.concurrentunit import ReservationStations, num_bits
 
-from ieee754.fpcommon.getop import FPADDBaseData
-from ieee754.fpcommon.pack import FPPackData
 from ieee754.fpcommon.normtopack import FPNormToPack
-
-
-from nmigen import Module, Signal, Elaboratable
-from math import log
-
-from ieee754.fpcommon.getop import FPPipeContext
-
 from ieee754.pipeline import PipelineSpec, DynamicPipe
 
 from ieee754.fcvt.float2int import FPCVTFloatToIntMod
@@ -29,6 +19,8 @@ from ieee754.fcvt.upsize import FPCVTUpConvertMod
 from ieee754.fcvt.downsize import FPCVTDownConvertMod
 
 
+# not used, yet
+# from nmigen import Signal
 class SignedOp:
     def __init__(self):
         self.signed = Signal(reset_less=True)
@@ -46,9 +38,10 @@ class FPCVTConvertDeNorm(DynamicPipe):
         sc = modkls(in_pspec, out_pspec)
         in_pspec.stage = sc
         super().__init__(in_pspec)
-        self.out = self.ospec(None)
 
 
+# this one is slightly weird-looking because of course the INT output
+# is, duh, an INT, so of course does not get "FP normalised".
 class FPCVTFtoIntBasePipe(ControlBase):
     def __init__(self, modkls, e_extra, in_pspec, out_pspec):
         ControlBase.__init__(self)
@@ -85,8 +78,8 @@ class FPCVTBasePipe(ControlBase):
 class FPCVTMuxInOutBase(ReservationStations):
     """ Reservation-Station version of FPCVT pipeline.
 
-        * fan-in on inputs (an array of FPADDBaseData: a,b,mid)
-        * 2-stage multiplier pipeline
+        * fan-in on inputs (an array of FPBaseData: a,b,mid)
+        * converter pipeline (alu)
         * fan-out on outputs (an array of FPPackData: z,mid)
 
         Fan-in and Fan-out are combinatorial.
@@ -103,16 +96,22 @@ class FPCVTMuxInOutBase(ReservationStations):
         self.alu = pkls(modkls, e_extra, self.in_pspec, self.out_pspec)
         ReservationStations.__init__(self, num_rows)
 
-    def i_specfn(self):
-        return FPADDBaseData(self.in_pspec)
 
-    def o_specfn(self):
-        return FPPackData(self.out_pspec)
+class FPCVTF2IntMuxInOut(FPCVTMuxInOutBase):
+    """ Reservation-Station version of FPCVT pipeline.
 
+        * fan-in on inputs (an array of FPBaseData: a,b,mid)
+        * 2-stage multiplier pipeline
+        * fan-out on outputs (an array of FPPackData: z,mid)
 
-def getkls(*args, **kwargs):
-    print ("getkls", args, kwargs)
-    return FPCVTMuxInOutBase(*args, **kwargs)
+        Fan-in and Fan-out are combinatorial.
+    """
+
+    def __init__(self, in_width, out_width, num_rows, op_wid=0):
+        FPCVTMuxInOutBase.__init__(self, FPCVTFloatToIntMod, False,
+                                         in_width, out_width,
+                                         num_rows, op_wid,
+                                         pkls=FPCVTFtoIntBasePipe)
 
 
 # factory which creates near-identical class structures that differ by
@@ -125,24 +124,12 @@ muxfactoryinput = [("FPCVTDownMuxInOut", FPCVTDownConvertMod, True, ),
                    ("FPCVTIntMuxInOut",   FPCVTIntToFloatMod,   True, ),
                   ]
 
+def getkls(*args, **kwargs):
+    print ("getkls", args, kwargs)
+    return FPCVTMuxInOutBase(*args, **kwargs)
+
 for (name, kls, e_extra) in muxfactoryinput:
     fn = functools.partial(getkls, kls, e_extra)
     setattr(sys.modules[__name__], name, fn)
 
 
-class FPCVTF2IntMuxInOut(FPCVTMuxInOutBase):
-    """ Reservation-Station version of FPCVT pipeline.
-
-        * fan-in on inputs (an array of FPADDBaseData: a,b,mid)
-        * 2-stage multiplier pipeline
-        * fan-out on outputs (an array of FPPackData: z,mid)
-
-        Fan-in and Fan-out are combinatorial.
-    """
-
-    def __init__(self, in_width, out_width, num_rows, op_wid=0):
-        FPCVTMuxInOutBase.__init__(self, FPCVTFloatToIntMod, False,
-                                         in_width, out_width,
-                                         num_rows, op_wid,
-                                         pkls=FPCVTFtoIntBasePipe)
-