convert to partition mask rather than partition points

[ieee754fpu.git] / src / ieee754 / fcvt / pipeline.py

diff --git a/src/ieee754/fcvt/pipeline.py b/src/ieee754/fcvt/pipeline.py
index 605bb16a65aa564560b9fae0acd66743da489e10..5e6cc19dee7f98c971d1ea7e2266339b4bf4d2ec 100644 (file)
--- a/src/ieee754/fcvt/pipeline.py
+++ b/src/ieee754/fcvt/pipeline.py
@@ -4,26 +4,13 @@ Copyright (C) 2019 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 
 """
 
-
 import sys
 import functools
 
-from nmigen import Module, Signal, Cat, Const, Mux, Elaboratable
-from nmigen.cli import main, verilog
-
 from nmutil.singlepipe import ControlBase
 from nmutil.concurrentunit import ReservationStations, num_bits
 
-from ieee754.fpcommon.getop import FPADDBaseData
-from ieee754.fpcommon.pack import FPPackData
 from ieee754.fpcommon.normtopack import FPNormToPack
-
-
-from nmigen import Module, Signal, Elaboratable
-from math import log
-
-from ieee754.fpcommon.getop import FPPipeContext
-
 from ieee754.pipeline import PipelineSpec, DynamicPipe
 
 from ieee754.fcvt.float2int import FPCVTFloatToIntMod
@@ -32,6 +19,8 @@ from ieee754.fcvt.upsize import FPCVTUpConvertMod
 from ieee754.fcvt.downsize import FPCVTDownConvertMod
 
 
+# not used, yet
+# from nmigen import Signal
 class SignedOp:
     def __init__(self):
         self.signed = Signal(reset_less=True)
@@ -49,9 +38,10 @@ class FPCVTConvertDeNorm(DynamicPipe):
         sc = modkls(in_pspec, out_pspec)
         in_pspec.stage = sc
         super().__init__(in_pspec)
-        self.out = self.ospec(None)
 
 
+# this one is slightly weird-looking because of course the INT output
+# is, duh, an INT, so of course does not get "FP normalised".
 class FPCVTFtoIntBasePipe(ControlBase):
     def __init__(self, modkls, e_extra, in_pspec, out_pspec):
         ControlBase.__init__(self)
@@ -88,8 +78,8 @@ class FPCVTBasePipe(ControlBase):
 class FPCVTMuxInOutBase(ReservationStations):
     """ Reservation-Station version of FPCVT pipeline.
 
-        * fan-in on inputs (an array of FPADDBaseData: a,b,mid)
-        * 2-stage multiplier pipeline
+        * fan-in on inputs (an array of FPBaseData: a,b,mid)
+        * converter pipeline (alu)
         * fan-out on outputs (an array of FPPackData: z,mid)
 
         Fan-in and Fan-out are combinatorial.
@@ -106,17 +96,11 @@ class FPCVTMuxInOutBase(ReservationStations):
         self.alu = pkls(modkls, e_extra, self.in_pspec, self.out_pspec)
         ReservationStations.__init__(self, num_rows)
 
-    def i_specfn(self):
-        return FPADDBaseData(self.in_pspec)
-
-    def o_specfn(self):
-        return FPPackData(self.out_pspec)
-
 
 class FPCVTF2IntMuxInOut(FPCVTMuxInOutBase):
     """ Reservation-Station version of FPCVT pipeline.
 
-        * fan-in on inputs (an array of FPADDBaseData: a,b,mid)
+        * fan-in on inputs (an array of FPBaseData: a,b,mid)
         * 2-stage multiplier pipeline
         * fan-out on outputs (an array of FPPackData: z,mid)