format code

[ieee754fpu.git] / src / ieee754 / fcvt / test / test_fcvt_pipe_32_16.py

diff --git a/src/ieee754/fcvt/test/test_fcvt_pipe_32_16.py b/src/ieee754/fcvt/test/test_fcvt_pipe_32_16.py
index 3117bf702c55c803a63a1e49602e61ccc4fd985b..8c803a75daaf6355f9e23ab17d34254d5b88ca2e 100644 (file)
--- a/src/ieee754/fcvt/test/test_fcvt_pipe_32_16.py
+++ b/src/ieee754/fcvt/test/test_fcvt_pipe_32_16.py
@@ -1,7 +1,7 @@
 """ test of FPCVTMuxInOut
 """
 
-from ieee754.fcvt.pipeline import (FPCVTDownMuxInOut,)
+from ieee754.fcvt.pipeline import FPCVTDownMuxInOut
 from ieee754.fpcommon.test.case_gen import run_pipe_fp
 from ieee754.fpcommon.test import unit_test_single
 from ieee754.fcvt.test.fcvt_data_32_16 import regressions
@@ -10,15 +10,17 @@ from sfpy import Float32, Float16
 
 import unittest
 
+
 def fcvt_16(x):
     return Float16(x)
 
+
 class TestFClassPipe(unittest.TestCase):
     def test_pipe_fp32_16(self):
         dut = FPCVTDownMuxInOut(32, 16, 4)
         run_pipe_fp(dut, 32, "fcvt", unit_test_single, Float32,
                     regressions, fcvt_16, 100, True)
 
+
 if __name__ == '__main__':
     unittest.main()
-