move FPModBase and FPModBaseChain to nmutil

[ieee754fpu.git] / src / ieee754 / fcvt / upsize.py

diff --git a/src/ieee754/fcvt/upsize.py b/src/ieee754/fcvt/upsize.py
index d8b9127e3cdffe6a89934e321656818fda456909..483ddbbc462a883a8ecf21285565a2d8ad1db3af 100644 (file)
--- a/src/ieee754/fcvt/upsize.py
+++ b/src/ieee754/fcvt/upsize.py
@@ -5,22 +5,22 @@
 import sys
 import functools
 
-from nmigen import Module, Signal, Cat, Const, Mux, Elaboratable
+from nmigen import Module, Signal, Cat
 from nmigen.cli import main, verilog
 
+from nmutil.pipemodbase import FPModBase
 from ieee754.fpcommon.getop import FPADDBaseData
 from ieee754.fpcommon.postcalc import FPAddStage1Data
 from ieee754.fpcommon.fpbase import FPNumDecode, FPNumBaseRecord
 
 
-class FPCVTUpConvertMod(Elaboratable):
+class FPCVTUpConvertMod(FPModBase):
     """ FP up-conversion (lower to higher bitwidth)
     """
     def __init__(self, in_pspec, out_pspec):
         self.in_pspec = in_pspec
         self.out_pspec = out_pspec
-        self.i = self.ispec()
-        self.o = self.ospec()
+        super().__init__(in_pspec, "upconvert")
 
     def ispec(self):
         return FPADDBaseData(self.in_pspec)
@@ -28,15 +28,6 @@ class FPCVTUpConvertMod(Elaboratable):
     def ospec(self):
         return FPAddStage1Data(self.out_pspec, e_extra=False)
 
-    def setup(self, m, i):
-        """ links module to inputs and outputs
-        """
-        m.submodules.upconvert = self
-        m.d.comb += self.i.eq(i)
-
-    def process(self, i):
-        return self.o
-
     def elaborate(self, platform):
         m = Module()
         comb = m.d.comb