finish adding all rounding modes to fadd -- formal proof passes

[ieee754fpu.git] / src / ieee754 / fpadd / add0.py

diff --git a/src/ieee754/fpadd/add0.py b/src/ieee754/fpadd/add0.py
index f7e77e4861953eea6ce691b711ea783a6502aabf..32c4fdf910309e45e6ba88c34cce4349430b2580 100644 (file)
--- a/src/ieee754/fpadd/add0.py
+++ b/src/ieee754/fpadd/add0.py
@@ -60,5 +60,6 @@ class FPAddStage0Mod(PipeModBase):
         comb += self.o.oz.eq(self.i.oz)
         comb += self.o.out_do_z.eq(self.i.out_do_z)
         comb += self.o.ctx.eq(self.i.ctx)
+        comb += self.o.rm.eq(self.i.rm)
 
         return m