-# IEEE Floating Point Adder (Single Precision)
-# Copyright (C) Jonathan P Dawson 2013
-# 2013-12-12
+"""IEEE754 Floating Point Adder Pipeline
-from nmigen import Module, Signal, Cat, Elaboratable
-from nmigen.cli import main, verilog
-
-from ieee754.fpcommon.fpbase import FPNumBase, FPNumBaseRecord
-from ieee754.fpcommon.fpbase import FPState
-from ieee754.fpcommon.denorm import FPSCData
-from ieee754.fpcommon.getop import FPPipeContext
+Copyright (C) 2019 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+"""
-class FPAddStage0Data:
+from nmigen import Module, Signal, Cat, Mux
+from nmigen.cli import main, verilog
- def __init__(self, width, pspec):
- self.z = FPNumBaseRecord(width, False)
- self.out_do_z = Signal(reset_less=True)
- self.oz = Signal(width, reset_less=True)
- self.tot = Signal(self.z.m_width + 4, reset_less=True)
- self.ctx = FPPipeContext(width, pspec)
- self.muxid = self.ctx.muxid
+from nmutil.pipemodbase import PipeModBase
- def eq(self, i):
- return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
- self.tot.eq(i.tot), self.ctx.eq(i.ctx)]
+from ieee754.fpcommon.denorm import FPSCData
+from ieee754.fpcommon.getop import FPPipeContext
+from ieee754.fpadd.datastruct import FPAddStage0Data
-class FPAddStage0Mod(Elaboratable):
+class FPAddStage0Mod(PipeModBase):
- def __init__(self, width, pspec):
- self.width = width
- self.pspec = pspec
- self.i = self.ispec()
- self.o = self.ospec()
+ def __init__(self, pspec):
+ super().__init__(pspec, "add0")
def ispec(self):
- return FPSCData(self.width, self.pspec, True)
+ return FPSCData(self.pspec, True)
def ospec(self):
- return FPAddStage0Data(self.width, self.pspec)
-
- def process(self, i):
- return self.o
-
- def setup(self, m, i):
- """ links module to inputs and outputs
- """
- m.submodules.add0 = self
- m.d.comb += self.i.eq(i)
+ return FPAddStage0Data(self.pspec)
def elaborate(self, platform):
m = Module()
- #m.submodules.add0_in_a = self.i.a
- #m.submodules.add0_in_b = self.i.b
- #m.submodules.add0_out_z = self.o.z
+ comb = m.d.comb
+ a = self.i.a
+ b = self.i.b
+ assert len(a.m) == len(b.m) # op lengths must be equal
# store intermediate tests (and zero-extended mantissas)
seq = Signal(reset_less=True)
mge = Signal(reset_less=True)
- am0 = Signal(len(self.i.a.m)+1, reset_less=True)
- bm0 = Signal(len(self.i.b.m)+1, reset_less=True)
- m.d.comb += [seq.eq(self.i.a.s == self.i.b.s),
- mge.eq(self.i.a.m >= self.i.b.m),
- am0.eq(Cat(self.i.a.m, 0)),
- bm0.eq(Cat(self.i.b.m, 0))
- ]
- # same-sign (both negative or both positive) add mantissas
- with m.If(~self.i.out_do_z):
- m.d.comb += self.o.z.e.eq(self.i.a.e)
- with m.If(seq):
- m.d.comb += [
- self.o.tot.eq(am0 + bm0),
- self.o.z.s.eq(self.i.a.s)
- ]
- # a mantissa greater than b, use a
- with m.Elif(mge):
- m.d.comb += [
- self.o.tot.eq(am0 - bm0),
- self.o.z.s.eq(self.i.a.s)
+ sm = Signal(reset_less=True)
+ op1 = Signal(len(a.m)+1, reset_less=True)
+ op2 = Signal(len(b.m)+1, reset_less=True)
+
+ # logic is as follows:
+ # * same-sign (both negative or both positive) add mantissas
+ # * opposite sign, subtract b mantissa from a
+ # * a mantissa greater than b, use a
+ # * b mantissa greater than a, use b
+ comb += [seq.eq(a.s == b.s),
+ mge.eq(a.m >= b.m),
+ sm.eq(seq | mge),
+ op1.eq(Cat(Mux(sm, a.m, b.m), 0)), # swap a and b
+ op2.eq(Cat(Mux(sm, b.m, a.m), 0)), # swap b and a
]
- # b mantissa greater than a, use b
- with m.Else():
- m.d.comb += [
- self.o.tot.eq(bm0 - am0),
- self.o.z.s.eq(self.i.b.s)
- ]
-
- m.d.comb += self.o.oz.eq(self.i.oz)
- m.d.comb += self.o.out_do_z.eq(self.i.out_do_z)
- m.d.comb += self.o.ctx.eq(self.i.ctx)
- return m
-
-class FPAddStage0(FPState):
- """ First stage of add. covers same-sign (add) and subtract
- special-casing when mantissas are greater or equal, to
- give greatest accuracy.
- """
+ # perform add into output z (s/m/e)
+ comb += self.o.z.e.eq(a.e) # exponent same
+ comb += self.o.z.s.eq(Mux(sm, a.s, b.s)) # sign swap
+ comb += self.o.tot.eq(Mux(seq, op1 + op2, op1 - op2)) # mantissa +/-
- def __init__(self, width, pspec):
- FPState.__init__(self, "add_0")
- self.mod = FPAddStage0Mod(width)
- self.o = self.mod.ospec()
+ # pass-through context
+ comb += self.o.oz.eq(self.i.oz)
+ comb += self.o.out_do_z.eq(self.i.out_do_z)
+ comb += self.o.ctx.eq(self.i.ctx)
+ comb += self.o.rm.eq(self.i.rm)
- def setup(self, m, i):
- """ links module to inputs and outputs
- """
- self.mod.setup(m, i)
-
- # NOTE: these could be done as combinatorial (merge add0+add1)
- m.d.sync += self.o.eq(self.mod.o)
-
- def action(self, m):
- m.next = "add_1"
+ return m
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