tidyup

[ieee754fpu.git] / src / ieee754 / fpadd / addstages.py

diff --git a/src/ieee754/fpadd/addstages.py b/src/ieee754/fpadd/addstages.py
index 76df0e872a71804ccd907d5b18095aa1cb5818ad..489365831b1bdde691a9c715cf5316fa05dc7d78 100644 (file)
--- a/src/ieee754/fpadd/addstages.py
+++ b/src/ieee754/fpadd/addstages.py
@@ -10,13 +10,13 @@ from nmigen.cli import main, verilog
 from nmutil.singlepipe import StageChain
 from ieee754.pipeline import DynamicPipe
 
-from ieee754.fpcommon.fpbase import FPState
 from ieee754.fpcommon.denorm import FPSCData
 from ieee754.fpcommon.postcalc import FPAddStage1Data
 from ieee754.fpadd.align import FPAddAlignSingleMod
 from ieee754.fpadd.add0 import FPAddStage0Mod
 from ieee754.fpadd.add1 import FPAddStage1Mod
 
+
 class FPAddAlignSingleAdd(DynamicPipe):
 
     def __init__(self, pspec):