elaboratable cases

[ieee754fpu.git] / src / ieee754 / fpadd / align.py

diff --git a/src/ieee754/fpadd/align.py b/src/ieee754/fpadd/align.py
index 381df1e5d7c38b44349c9b93c2cc176ed82d141f..0bb75e0aaa680a37f302797241e05729aab7f7f9 100644 (file)
--- a/src/ieee754/fpadd/align.py
+++ b/src/ieee754/fpadd/align.py
@@ -2,7 +2,7 @@
 # Copyright (C) Jonathan P Dawson 2013
 # 2013-12-12
 
-from nmigen import Module, Signal
+from nmigen import Module, Signal, Elaboratable
 from nmigen.cli import main, verilog
 
 from ieee754.fpcommon.fpbase import FPNumOut, FPNumIn, FPNumBase
@@ -93,7 +93,7 @@ class FPAddAlignMulti(FPState):
             m.next = "add_0"
 
 
-class FPAddAlignSingleMod:
+class FPAddAlignSingleMod(Elaboratable):
 
     def __init__(self, width, id_wid):
         self.width = width