id_wid (muxid bitwidth) based on num_rows, not the data width

[ieee754fpu.git] / src / ieee754 / fpadd / pipeline.py

diff --git a/src/ieee754/fpadd/pipeline.py b/src/ieee754/fpadd/pipeline.py
index 5d622132d317f55a8beed143209d3b0bea57781f..424d39e74a6e61f01cc7b3f2e1cd657d84e1614e 100644 (file)
--- a/src/ieee754/fpadd/pipeline.py
+++ b/src/ieee754/fpadd/pipeline.py
@@ -84,7 +84,7 @@ class FPADDMuxInOut(ReservationStations):
     """
 
     def __init__(self, width, num_rows, op_wid=None):
-        self.id_wid = num_bits(width)
+        self.id_wid = num_bits(num_rows)
         self.op_wid = op_wid
         self.pspec = PipelineSpec(width, self.id_wid, op_wid)
         self.alu = FPADDBasePipe(self.pspec)