add comments

[ieee754fpu.git] / src / ieee754 / fpadd / pipeline.py

diff --git a/src/ieee754/fpadd/pipeline.py b/src/ieee754/fpadd/pipeline.py
index 9c51c3ca55df2f80c612a670ab8ea7e2f12a51c6..5d622132d317f55a8beed143209d3b0bea57781f 100644 (file)
--- a/src/ieee754/fpadd/pipeline.py
+++ b/src/ieee754/fpadd/pipeline.py
@@ -30,6 +30,12 @@ normpack  - FPNormToPack           ispec FPAddStage1Data
                             CorrectionsMod,
                             PackMod
 
+This pipeline has a 3 clock latency, and, with the separation into
+separate "modules", it is quite clear how to create longer-latency
+pipelines (if needed) - just create a new, longer top-level (FPADDBasePipe
+alternative) and construct shorter pipe stages using the building blocks,
+RoundMod, FPAddStage0Mod etc.
+
 """
 
 from nmigen import Module