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[ieee754fpu.git] / src / ieee754 / fpadd / pipeline.py

diff --git a/src/ieee754/fpadd/pipeline.py b/src/ieee754/fpadd/pipeline.py
index 1458dfefc0a391c5feb62f6d04a87534790e4048..5d622132d317f55a8beed143209d3b0bea57781f 100644 (file)
--- a/src/ieee754/fpadd/pipeline.py
+++ b/src/ieee754/fpadd/pipeline.py
@@ -1,6 +1,42 @@
-# IEEE Floating Point Adder (Single Precision)
-# Copyright (C) Jonathan P Dawson 2013
-# 2013-12-12
+"""IEEE Floating Point Adder Pipeline
+
+Relevant bugreport: http://bugs.libre-riscv.org/show_bug.cgi?id=75
+
+Stack looks like this:
+
+* scnorm    - FPMulSpecialCasesDeNorm
+* addalign  - FPAddAlignSingleAdd
+* normpack  - FPNormToPack
+
+scnorm   - FPDIVSpecialCasesDeNorm ispec FPADDBaseData
+------                             ospec FPSCData
+
+                StageChain: FPMULSpecialCasesMod,
+                            FPAddDeNormMod
+                            FPAlignModSingle
+
+addalign  - FPAddAlignSingleAdd    ispec FPSCData
+--------                           ospec FPAddStage1Data
+
+                StageChain: FPAddAlignSingleMod
+                            FPAddStage0Mod
+                            FPAddStage1Mod
+
+normpack  - FPNormToPack           ispec FPAddStage1Data
+--------                           ospec FPPackData
+
+                StageChain: Norm1ModSingle,
+                            RoundMod,
+                            CorrectionsMod,
+                            PackMod
+
+This pipeline has a 3 clock latency, and, with the separation into
+separate "modules", it is quite clear how to create longer-latency
+pipelines (if needed) - just create a new, longer top-level (FPADDBasePipe
+alternative) and construct shorter pipe stages using the building blocks,
+RoundMod, FPAddStage0Mod etc.
+
+"""
 
 from nmigen import Module
 from nmigen.cli import main, verilog
@@ -16,15 +52,15 @@ from ieee754.fpcommon.pack import FPPackData
 from ieee754.fpcommon.normtopack import FPNormToPack
 from .specialcases import FPAddSpecialCasesDeNorm
 from .addstages import FPAddAlignSingleAdd
-
+from ieee754.pipeline import PipelineSpec
 
 
 class FPADDBasePipe(ControlBase):
-    def __init__(self, width, id_wid):
+    def __init__(self, pspec):
         ControlBase.__init__(self)
-        self.pipe1 = FPAddSpecialCasesDeNorm(width, id_wid)
-        self.pipe2 = FPAddAlignSingleAdd(width, id_wid)
-        self.pipe3 = FPNormToPack(width, id_wid)
+        self.pipe1 = FPAddSpecialCasesDeNorm(pspec)
+        self.pipe2 = FPAddAlignSingleAdd(pspec)
+        self.pipe3 = FPNormToPack(pspec)
 
         self._eqs = self.connect([self.pipe1, self.pipe2, self.pipe3])
 
@@ -46,15 +82,16 @@ class FPADDMuxInOut(ReservationStations):
 
         Fan-in and Fan-out are combinatorial.
     """
+
     def __init__(self, width, num_rows, op_wid=None):
-        self.width = width
         self.id_wid = num_bits(width)
         self.op_wid = op_wid
-        self.alu = FPADDBasePipe(width, self.id_wid)
+        self.pspec = PipelineSpec(width, self.id_wid, op_wid)
+        self.alu = FPADDBasePipe(self.pspec)
         ReservationStations.__init__(self, num_rows)
 
     def i_specfn(self):
-        return FPADDBaseData(self.width, self.id_wid, self.op_wid)
+        return FPADDBaseData(self.pspec)
 
     def o_specfn(self):
-        return FPPackData(self.width, self.id_wid, self.op_wid)
+        return FPPackData(self.pspec)