add fsub support to fadd pipeline

[ieee754fpu.git] / src / ieee754 / fpadd / statemachine.py

diff --git a/src/ieee754/fpadd/statemachine.py b/src/ieee754/fpadd/statemachine.py
index 918e35a2d81ff4a6d9220918b7fec8ef998208ce..efc2ebc61dc92eb86a0635f7de3e23cf61136a65 100644 (file)
--- a/src/ieee754/fpadd/statemachine.py
+++ b/src/ieee754/fpadd/statemachine.py
@@ -8,12 +8,12 @@ from math import log
 
 from ieee754.fpcommon.fpbase import FPOpIn, FPOpOut
 from ieee754.fpcommon.fpbase import Trigger
-from nmutil.singlepipe import (StageChain, SimpleHandshake)
+from nmutil.singlepipe import StageChain
 
 from ieee754.fpcommon.fpbase import FPState, FPID
-from ieee754.fpcommon.getop import (FPGetOp, FPADDBaseData, FPGet2Op)
+from ieee754.fpcommon.getop import (FPGetOp, FPBaseData, FPGet2Op)
 from ieee754.fpcommon.denorm import (FPSCData, FPAddDeNorm)
-from ieee754.fpcommon.postcalc import FPAddStage1Data
+from ieee754.fpcommon.postcalc import FPPostCalcData
 from ieee754.fpcommon.postnormalise import (FPNorm1Data,
                             FPNorm1Single, FPNorm1Multi)
 from ieee754.fpcommon.roundz import (FPRoundData, FPRound)
@@ -33,14 +33,14 @@ class FPOpData:
     def __init__(self, width, id_wid):
         self.z = FPOpOut(width)
         self.z.data_o = Signal(width)
-        self.mid = Signal(id_wid, reset_less=True)
+        self.muxid = Signal(id_wid, reset_less=True)
 
     def __iter__(self):
         yield self.z
-        yield self.mid
+        yield self.muxid
 
     def eq(self, i):
-        return [self.z.eq(i.z), self.mid.eq(i.mid)]
+        return [self.z.eq(i.z), self.muxid.eq(i.mid)]
 
     def ports(self):
         return list(self)
@@ -68,7 +68,7 @@ class FPADDBaseMod(Elaboratable):
         self.states = []
 
     def ispec(self):
-        return FPADDBaseData(self.width, self.id_wid)
+        return FPBaseData(self.width, self.id_wid)
 
     def ospec(self):
         return FPOpData(self.width, self.id_wid)
@@ -161,7 +161,7 @@ class FPADDBaseMod(Elaboratable):
         get.trigger_setup(m, self.in_t.stb, self.in_t.ack)
 
         chainlist = [get, sc, alm, n1]
-        chain = StageChain(chainlist, specallocate=True)
+        chain = StageChain(chainlist, specallocate=False)
         chain.setup(m, self.i)
         m.submodules.sc = sc
         m.submodules.alm = alm