finish adding all rounding modes to fadd -- formal proof passes

[ieee754fpu.git] / src / ieee754 / fpcommon / basedata.py

diff --git a/src/ieee754/fpcommon/basedata.py b/src/ieee754/fpcommon/basedata.py
index 197ae96f3f0fe07199471db7f0c382ae21e7c7ef..c6be83f31d3dbca3e68e02e078764aae80fb4438 100644 (file)
--- a/src/ieee754/fpcommon/basedata.py
+++ b/src/ieee754/fpcommon/basedata.py
@@ -2,6 +2,7 @@
 # Copyright (C) 2019 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 
 from nmigen import Signal
+from ieee754.fpcommon.fpbase import FPRoundingMode
 from ieee754.fpcommon.getop import FPPipeContext
 
 
@@ -20,17 +21,22 @@ class FPBaseData:
         self.muxid = self.ctx.muxid # make muxid available here: complicated
         self.ops = ops
 
+        self.rm = Signal(FPRoundingMode, reset=FPRoundingMode.DEFAULT)
+        """rounding mode"""
+
     def eq(self, i):
         ret = []
         for op1, op2 in zip(self.ops, i.ops):
             ret.append(op1.eq(op2))
         ret.append(self.ctx.eq(i.ctx))
+        ret.append(self.rm.eq(i.rm))
         return ret
 
     def __iter__(self):
         if self.ops:
             yield from self.ops
         yield from self.ctx
+        yield self.rm
 
     def ports(self):
         return list(self)