add fpclass pipeline (1st version)

[ieee754fpu.git] / src / ieee754 / fpcommon / pack.py

diff --git a/src/ieee754/fpcommon/pack.py b/src/ieee754/fpcommon/pack.py
index e03edd4fcbfb612441f9bb864f941f2ce8e52e21..1240ca62e42be0aa7c414f7373dc92e19adfdda8 100644 (file)
--- a/src/ieee754/fpcommon/pack.py
+++ b/src/ieee754/fpcommon/pack.py
@@ -9,32 +9,48 @@ from ieee754.fpcommon.fpbase import FPNumOut, FPNumBaseRecord, FPNumBase
 from ieee754.fpcommon.fpbase import FPState
 from .roundz import FPRoundData
 from nmutil.singlepipe import Object
-from ieee754.fpcommon.getop import FPBaseData
+from ieee754.fpcommon.getop import FPPipeContext
 
 
-class FPPackData(Object):
+class FPPackData:
 
-    def __init__(self, width, id_wid, op_wid):
-        Object.__init__(self)
+    def __init__(self, pspec):
+        width = pspec.width
         self.z = Signal(width, reset_less=True)    # result
-        self.mid = Signal(id_wid, reset_less=True) # multiplex ID
-        self.op = Signal(op_wid or 0, reset_less=True) # operand width
+        self.ctx = FPPipeContext(pspec)
+
+        # this is complicated: it's a workaround, due to the
+        # array-indexing not working properly in nmigen.
+        # self.ports() is used to access the ArrayProxy objects by name,
+        # however it doesn't work recursively.  the workaround:
+        # drop the sub-objects into *this* scope and they can be
+        # accessed / set.  it's horrible.
+        self.muxid = self.ctx.muxid
+        self.op = self.ctx.op
+
+    def eq(self, i):
+        return [self.z.eq(i.z), self.ctx.eq(i.ctx)]
+
+    def __iter__(self):
+        yield self.z
+        yield from self.ctx
+
+    def ports(self):
+        return list(self)
 
 
 class FPPackMod(Elaboratable):
 
-    def __init__(self, width, id_wid, op_wid=None):
-        self.width = width
-        self.id_wid = id_wid
-        self.op_wid = op_wid
+    def __init__(self, pspec):
+        self.pspec = pspec
         self.i = self.ispec()
         self.o = self.ospec()
 
     def ispec(self):
-        return FPRoundData(self.width, self.id_wid, self.op_wid)
+        return FPRoundData(self.pspec)
 
     def ospec(self):
-        return FPPackData(self.width, self.id_wid, self.op_wid)
+        return FPPackData(self.pspec)
 
     def process(self, i):
         return self.o
@@ -47,12 +63,10 @@ class FPPackMod(Elaboratable):
 
     def elaborate(self, platform):
         m = Module()
-        z = FPNumBaseRecord(self.width, False)
+        z = FPNumBaseRecord(self.pspec.width, False)
         m.submodules.pack_in_z = in_z = FPNumBase(self.i.z)
         #m.submodules.pack_out_z = out_z = FPNumOut(z)
-        m.d.comb += self.o.mid.eq(self.i.mid)
-        if self.i.op_wid:
-            m.d.comb += self.o.op.eq(self.i.op)
+        m.d.comb += self.o.ctx.eq(self.i.ctx)
         with m.If(~self.i.out_do_z):
             with m.If(in_z.is_overflowed):
                 m.d.comb += z.inf(self.i.z.s)
@@ -83,7 +97,7 @@ class FPPack(FPState):
         self.mod.setup(m, in_z)
 
         m.d.sync += self.out_z.v.eq(self.mod.out_z.v)
-        m.d.sync += self.out_z.mid.eq(self.mod.o.mid)
+        m.d.sync += self.out_z.ctx.eq(self.mod.o.ctx)
 
     def action(self, m):
         m.next = "pack_put_z"