move FPModBase and FPModBaseChain to nmutil

[ieee754fpu.git] / src / ieee754 / fpcommon / pack.py

diff --git a/src/ieee754/fpcommon/pack.py b/src/ieee754/fpcommon/pack.py
index 7fe1a7c7490ad196418ee294a791e5020d636d11..4553f53182edb8df91b01aa84e9e32062e759dc5 100644 (file)
--- a/src/ieee754/fpcommon/pack.py
+++ b/src/ieee754/fpcommon/pack.py
@@ -2,84 +2,69 @@
 # Copyright (C) Jonathan P Dawson 2013
 # 2013-12-12
 
-from nmigen import Module, Signal, Elaboratable
+from nmigen import Module, Signal
 from nmigen.cli import main, verilog
 
-from ieee754.fpcommon.fpbase import FPNumOut, FPNumBaseRecord, FPNumBase
-from ieee754.fpcommon.fpbase import FPState
-from .roundz import FPRoundData
-from nmutil.singlepipe import Object
+from nmutil.pipemodbase import FPModBase
+from ieee754.fpcommon.fpbase import FPNumBaseRecord, FPNumBase
+from ieee754.fpcommon.roundz import FPRoundData
 from ieee754.fpcommon.getop import FPPipeContext
 
 
-class FPPackData(Object):
+class FPPackData:
 
-    def __init__(self, width, pspec):
-        Object.__init__(self)
+    def __init__(self, pspec):
+        width = pspec.width
         self.z = Signal(width, reset_less=True)    # result
-        self.ctx = FPPipeContext(width, pspec)
+        self.ctx = FPPipeContext(pspec)
+
+        # this is complicated: it's a workaround, due to the
+        # array-indexing not working properly in nmigen.
+        # self.ports() is used to access the ArrayProxy objects by name,
+        # however it doesn't work recursively.  the workaround:
+        # drop the sub-objects into *this* scope and they can be
+        # accessed / set.  it's horrible.
         self.muxid = self.ctx.muxid
+        self.op = self.ctx.op
 
-class FPPackMod(Elaboratable):
+    def eq(self, i):
+        return [self.z.eq(i.z), self.ctx.eq(i.ctx)]
 
-    def __init__(self, width, pspec):
-        self.width = width
-        self.pspec = pspec
-        self.i = self.ispec()
-        self.o = self.ospec()
+    def __iter__(self):
+        yield self.z
+        yield from self.ctx
 
-    def ispec(self):
-        return FPRoundData(self.width, self.pspec)
+    def ports(self):
+        return list(self)
 
-    def ospec(self):
-        return FPPackData(self.width, self.pspec)
 
-    def process(self, i):
-        return self.o
+class FPPackMod(FPModBase):
 
-    def setup(self, m, in_z):
-        """ links module to inputs and outputs
-        """
-        m.submodules.pack = self
-        m.d.comb += self.i.eq(in_z)
+    def __init__(self, pspec):
+        super().__init__(pspec, "pack")
+
+    def ispec(self):
+        return FPRoundData(self.pspec)
+
+    def ospec(self):
+        return FPPackData(self.pspec)
 
     def elaborate(self, platform):
         m = Module()
-        z = FPNumBaseRecord(self.width, False)
+        comb = m.d.comb
+
+        z = FPNumBaseRecord(self.pspec.width, False, name="z")
         m.submodules.pack_in_z = in_z = FPNumBase(self.i.z)
-        #m.submodules.pack_out_z = out_z = FPNumOut(z)
-        m.d.comb += self.o.ctx.eq(self.i.ctx)
+
         with m.If(~self.i.out_do_z):
             with m.If(in_z.is_overflowed):
-                m.d.comb += z.inf(self.i.z.s)
+                comb += z.inf(self.i.z.s)
             with m.Else():
-                m.d.comb += z.create(self.i.z.s, self.i.z.e, self.i.z.m)
+                comb += z.create(self.i.z.s, self.i.z.e, self.i.z.m)
         with m.Else():
-            m.d.comb += z.v.eq(self.i.oz)
-        m.d.comb += self.o.z.eq(z.v)
-        return m
+            comb += z.v.eq(self.i.oz)
 
+        comb += self.o.ctx.eq(self.i.ctx)
+        comb += self.o.z.eq(z.v)
 
-class FPPack(FPState):
-
-    def __init__(self, width, id_wid):
-        FPState.__init__(self, "pack")
-        self.mod = FPPackMod(width)
-        self.out_z = self.ospec()
-
-    def ispec(self):
-        return self.mod.ispec()
-
-    def ospec(self):
-        return self.mod.ospec()
-
-    def setup(self, m, in_z):
-        """ links module to inputs and outputs
-        """
-        self.mod.setup(m, in_z)
-
-        m.d.sync += self.out_z.v.eq(self.mod.out_z.v)
-        m.d.sync += self.out_z.ctx.eq(self.mod.o.ctx)
-
-    def action(self, m):
-        m.next = "pack_put_z"
+        return m