rewrote the logic in div[02].py; fdiv/fsqrt/frsqrt all works!

[ieee754fpu.git] / src / ieee754 / fpcommon / postcalc.py

diff --git a/src/ieee754/fpcommon/postcalc.py b/src/ieee754/fpcommon/postcalc.py
index ce7b273683437f3c266ff782cf356145130edd99..fc906a2d124de007428111243433a0ab4b6af042 100644 (file)
--- a/src/ieee754/fpcommon/postcalc.py
+++ b/src/ieee754/fpcommon/postcalc.py
@@ -6,11 +6,12 @@ from nmigen import Signal
 from ieee754.fpcommon.fpbase import Overflow, FPNumBaseRecord
 from ieee754.fpcommon.getop import FPPipeContext
 
+
 class FPAddStage1Data:
 
     def __init__(self, pspec, e_extra=False):
         width = pspec.width
-        self.z = FPNumBaseRecord(width, False, e_extra)
+        self.z = FPNumBaseRecord(width, False, e_extra, name="z")
         self.out_do_z = Signal(reset_less=True)
         self.oz = Signal(width, reset_less=True)
         self.of = Overflow()