from ieee754.fpcommon.fpbase import (Overflow, OverflowMod,
FPNumBase, FPNumBaseRecord)
-from ieee754.fpcommon.fpbase import MultiShiftRMerge
from ieee754.fpcommon.fpbase import FPState
from ieee754.fpcommon.getop import FPPipeContext
from ieee754.fpcommon.msbhigh import FPMSBHigh
+from ieee754.fpcommon.exphigh import FPEXPHigh
from .postcalc import FPAddStage1Data
def __init__(self, pspec):
width = pspec.width
self.roundz = Signal(reset_less=True, name="norm1_roundz")
- self.z = FPNumBaseRecord(width, False)
+ self.z = FPNumBaseRecord(width, False, name="z")
self.out_do_z = Signal(reset_less=True)
self.oz = Signal(width, reset_less=True)
self.ctx = FPPipeContext(pspec)
def eq(self, i):
ret = [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
- self.roundz.eq(i.roundz), self.ctx.eq(i.ctx)]
+ self.roundz.eq(i.roundz), self.ctx.eq(i.ctx)]
return ret
espec = (len(insel_z.e), True)
mwid = self.o.z.m_width+2
- ediff_n126 = Signal(espec, reset_less=True)
- msr = MultiShiftRMerge(mwid+2, espec)
- m.submodules.multishift_r = msr
+ msr = FPEXPHigh(mwid+2, espec[0])
+ m.submodules.norm_exp = msr
msb = FPMSBHigh(mwid+1, espec[0], True)
m.submodules.norm_msb = msb
m.d.comb += increase.eq(insel_z.exp_lt_n126)
# decrease exponent
with m.If(~self.i.out_do_z):
+ # concatenate s/r/g with mantissa
+ temp_m = Signal(mwid+2, reset_less=True)
+ m.d.comb += temp_m.eq(Cat(i.of.sticky, i.of.round_bit, i.of.guard,
+ insel_z.m)),
+
with m.If(decrease):
# make sure that the amount to decrease by does NOT
# go below the minimum non-INF/NaN exponent
m.d.comb += msb.limclz.eq(insel_z.exp_sub_n126)
m.d.comb += [
- # cat round and guard bits back into the mantissa
- msb.m_in.eq(Cat(i.of.sticky, i.of.round_bit, i.of.guard,
- insel_z.m)),
+ # inputs: mantissa and exponent
+ msb.m_in.eq(temp_m),
msb.e_in.eq(insel_z.e),
- self.o.z.e.eq(msb.e_out),
+
+ # outputs: mantissa first (s/r/g/m[3:])
self.o.z.m.eq(msb.m_out[3:]), # exclude bits 0&1
of.m0.eq(msb.m_out[3]), # copy of mantissa[0]
# overflow in bits 0..1: got shifted too (leave sticky)
of.guard.eq(msb.m_out[2]), # guard
of.round_bit.eq(msb.m_out[1]), # round
+ # now exponent out
+ self.o.z.e.eq(msb.e_out),
]
# increase exponent
with m.Elif(increase):
- temp_m = Signal(mwid+1, reset_less=True)
+ ediff_n126 = Signal(espec, reset_less=True)
m.d.comb += [
- temp_m.eq(Cat(i.of.sticky, i.of.round_bit, i.of.guard,
- insel_z.m)),
+ # concatenate
ediff_n126.eq(insel_z.fp.N126 - insel_z.e),
- # connect multi-shifter to inp/out mantissa (and ediff)
- msr.inp.eq(temp_m),
- msr.diff.eq(ediff_n126),
- self.o.z.m.eq(msr.m[3:]),
- of.m0.eq(msr.m[3]), # copy of mantissa[0]
- # overflow in bits 0..1: got shifted too (leave sticky)
- of.guard.eq(msr.m[2]), # guard
- of.round_bit.eq(msr.m[1]), # round
- of.sticky.eq(msr.m[0]), # sticky
- self.o.z.e.eq(insel_z.e + ediff_n126),
+ # connect multi-shifter to inp/out m/e (and ediff)
+ msr.m_in.eq(temp_m),
+ msr.e_in.eq(insel_z.e),
+ msr.ediff.eq(ediff_n126),
+
+ # outputs: mantissa first (s/r/g/m[3:])
+ self.o.z.m.eq(msr.m_out[3:]),
+ of.m0.eq(msr.m_out[3]), # copy of mantissa[0]
+ # overflow in bits 0..2: got shifted too (leave sticky)
+ of.guard.eq(msr.m_out[2]), # guard
+ of.round_bit.eq(msr.m_out[1]), # round
+ of.sticky.eq(msr.m_out[0]), # sticky
+ # now exponent
+ self.o.z.e.eq(msr.e_out),
]
m.d.comb += self.o.roundz.eq(of.roundz_out)
increase = Signal(reset_less=True)
m.d.comb += decrease.eq(in_z.m_msbzero & in_z.exp_gt_n126)
m.d.comb += increase.eq(in_z.exp_lt_n126)
- m.d.comb += self.out_norm.eq(decrease | increase) # loop-end
+ m.d.comb += self.out_norm.eq(decrease | increase) # loop-end
# decrease exponent
with m.If(decrease):
m.d.comb += [
self.out_z.e.eq(in_z.e - 1), # DECREASE exponent
- self.out_z.m.eq(in_z.m << 1), # shift mantissa UP
- self.out_z.m[0].eq(in_of.guard), # steal guard (was tot[2])
- self.out_of.guard.eq(in_of.round_bit), # round (was tot[1])
+ self.out_z.m.eq(in_z.m << 1), # shift mantissa UP
+ self.out_z.m[0].eq(in_of.guard), # steal guard (was tot[2])
+ self.out_of.guard.eq(in_of.round_bit), # round (was tot[1])
self.out_of.round_bit.eq(0), # reset round bit
self.out_of.m0.eq(in_of.guard),
]
with m.Elif(increase):
m.d.comb += [
self.out_z.e.eq(in_z.e + 1), # INCREASE exponent
- self.out_z.m.eq(in_z.m >> 1), # shift mantissa DOWN
+ self.out_z.m.eq(in_z.m >> 1), # shift mantissa DOWN
self.out_of.guard.eq(in_z.m[0]),
self.out_of.m0.eq(in_z.m[1]),
self.out_of.round_bit.eq(in_of.guard),
self.out_z, self.out_norm)
m.d.comb += self.stb.eq(norm_stb)
- m.d.sync += self.ack.eq(0) # sets to zero when not in normalise_1 state
+ # sets to zero when not in normalise_1 state
+ m.d.sync += self.ack.eq(0)
def action(self, m):
m.d.comb += self.in_accept.eq((~self.ack) & (self.stb))
m.next = "round"
m.d.sync += self.ack.eq(1)
m.d.sync += self.out_roundz.eq(self.mod.out_of.roundz)
-
-
projects / ieee754fpu.git / blobdiff