finish adding all rounding modes to fadd -- formal proof passes

[ieee754fpu.git] / src / ieee754 / fpcommon / pscdata.py

diff --git a/src/ieee754/fpcommon/pscdata.py b/src/ieee754/fpcommon/pscdata.py
index da449d27460ca05a0686fb5f7bd344ad0459f130..7bf22e943bcfe0e2fdbb23aa6ddbe38dcb89d8c5 100644 (file)
--- a/src/ieee754/fpcommon/pscdata.py
+++ b/src/ieee754/fpcommon/pscdata.py
@@ -5,7 +5,7 @@ Copyright (C) 2019 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 """
 
 from nmigen import Signal
-from ieee754.fpcommon.fpbase import FPNumBaseRecord
+from ieee754.fpcommon.fpbase import FPNumBaseRecord, FPRoundingMode
 from ieee754.fpcommon.getop import FPPipeContext
 
 
@@ -25,6 +25,9 @@ class FPSCData:
         self.ctx = FPPipeContext(pspec)
         self.muxid = self.ctx.muxid
 
+        self.rm = Signal(FPRoundingMode, reset=FPRoundingMode.DEFAULT)
+        """rounding mode"""
+
     def __iter__(self):
         yield from self.a
         yield from self.b
@@ -32,8 +35,10 @@ class FPSCData:
         yield self.oz
         yield self.out_do_z
         yield from self.ctx
+        yield self.rm
 
     def eq(self, i):
         ret = [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
-               self.a.eq(i.a), self.b.eq(i.b), self.ctx.eq(i.ctx)]
+               self.a.eq(i.a), self.b.eq(i.b), self.ctx.eq(i.ctx),
+               self.rm.eq(i.rm)]
         return ret