from nmigen import Module, Signal, Elaboratable
from nmigen.cli import main, verilog
-from fpbase import FPNumBase
-from fpbase import FPState
-from fpcommon.postnormalise import FPNorm1Data
+from ieee754.fpcommon.fpbase import FPNumBase, FPNumBaseRecord
+from ieee754.fpcommon.fpbase import FPState
+from ieee754.fpcommon.getop import FPPipeContext
+from .postnormalise import FPNorm1Data
class FPRoundData:
- def __init__(self, width, id_wid):
- self.z = FPNumBase(width, False)
+ def __init__(self, width, pspec):
+ self.z = FPNumBaseRecord(width, False)
+ self.ctx = FPPipeContext(width, pspec)
+ self.muxid = self.ctx.muxid
+ # pipeline bypass [data comes from specialcases]
self.out_do_z = Signal(reset_less=True)
self.oz = Signal(width, reset_less=True)
- self.mid = Signal(id_wid, reset_less=True)
def eq(self, i):
- return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
- self.mid.eq(i.mid)]
+ ret = [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
+ self.ctx.eq(i.ctx)]
+ return ret
class FPRoundMod(Elaboratable):
- def __init__(self, width, id_wid):
+ def __init__(self, width, pspec):
self.width = width
- self.id_wid = id_wid
+ self.pspec = pspec
self.i = self.ispec()
self.out_z = self.ospec()
def ispec(self):
- return FPNorm1Data(self.width, self.id_wid)
+ return FPNorm1Data(self.width, self.pspec)
def ospec(self):
- return FPRoundData(self.width, self.id_wid)
+ return FPRoundData(self.width, self.pspec)
def process(self, i):
return self.out_z
def elaborate(self, platform):
m = Module()
m.d.comb += self.out_z.eq(self.i) # copies mid, z, out_do_z
- with m.If(~self.i.out_do_z):
+ with m.If(~self.i.out_do_z): # bypass wasn't enabled
with m.If(self.i.roundz):
m.d.comb += self.out_z.z.m.eq(self.i.z.m + 1) # mantissa up
with m.If(self.i.z.m == self.i.z.m1s): # all 1s
self.idsync(m)
m.d.sync += self.out_z.eq(self.mod.out_z)
- m.d.sync += self.out_z.mid.eq(self.mod.o.mid)
+ m.d.sync += self.out_z.ctx.eq(self.mod.o.ctx)
def action(self, m):
m.next = "corrections"