weirdness on INT32->FP32 detected. ui32/i32->f32 test added

[ieee754fpu.git] / src / ieee754 / fpcommon / test / fpmux.py

diff --git a/src/ieee754/fpcommon/test/fpmux.py b/src/ieee754/fpcommon/test/fpmux.py
index 273c80253fe9db0d78a3310de898d1042a3200c9..181e57a2dac5e8c9e9cfeb338968c1330726fb30 100644 (file)
--- a/src/ieee754/fpcommon/test/fpmux.py
+++ b/src/ieee754/fpcommon/test/fpmux.py
@@ -11,11 +11,12 @@ from nmigen.cli import verilog, rtlil
 
 
 class MuxInOut:
-    def __init__(self, dut, width, fpkls, fpop, vals, single_op):
+    def __init__(self, dut, width, fpkls, fpop, vals, single_op, opcode):
         self.dut = dut
         self.fpkls = fpkls
         self.fpop = fpop
         self.single_op = single_op
+        self.opcode = opcode
         self.di = {}
         self.do = {}
         self.tlen = len(vals) // dut.num_rows
@@ -25,7 +26,11 @@ class MuxInOut:
             self.do[muxid] = []
             for i in range(self.tlen):
                 if self.single_op:
-                    (op1, ) = vals.pop(0)
+                    #print ("vals", vals)
+                    op1 = vals.pop(0)
+                    if isinstance(op1, tuple):
+                        assert len(op1) == 1
+                        op1 = op1[0]
                     res = self.fpop(self.fpkls(op1))
                     self.di[muxid][i] = (op1, )
                 else:
@@ -44,6 +49,8 @@ class MuxInOut:
             rs = self.dut.p[muxid]
             yield rs.valid_i.eq(1)
             yield rs.data_i.a.eq(op1)
+            if self.opcode is not None:
+                yield rs.data_i.ctx.op.eq(self.opcode)
             if not self.single_op:
                 yield rs.data_i.b.eq(op2)
             yield rs.data_i.muxid.eq(muxid)
@@ -142,6 +149,20 @@ def create_random(num_rows, width, single_op=False, n_vals=10):
                 #op1 = 0x3340f2a7
                 #op1 = 0x33D6BF95
                 #op1 = 0x9885020648d8c0e8
+                #op1 = 0xc26b
+                #op1 = 3
+
+                #op1 = 0x3a66
+                #op1 = 0x5299
+                #op1 = 0xe0eb
+                #op1 = 0x3954
+                #op1 = 0x4dea
+                #op1 = 0x65eb
+
+                #op1 = 0x1841
+
+                #op1 = 0x3449f9a9
+
                 vals.append((op1,))
             else:
                 op1 = randint(0, (1<<width)-1)
@@ -157,20 +178,23 @@ def repeat(num_rows, vals):
     """
     vals = list(vals)
     n_to_repeat = len(vals) % num_rows
-    print (vals, vals[-1])
+    #print ("repeat", vals)
     return vals + [vals[-1]] * n_to_repeat
 
 
-def pipe_cornercases_repeat(dut, name, mod, fmod, width, fn, cc, fpfn, count):
+def pipe_cornercases_repeat(dut, name, mod, fmod, width, fn, cc, fpfn, count,
+                            single_op=False):
     for i, fixed_num in enumerate(cc(mod)):
-        vals = fn(mod, fixed_num, count, width)
+        vals = fn(mod, fixed_num, count, width, single_op)
         vals = repeat(dut.num_rows, vals)
+        #print ("repeat", i, fn, single_op, list(vals))
         fmt = "test_pipe_fp%d_%s_cornercases_%d"
         runfp(dut, width, fmt % (width, name, i),
-                   fmod, fpfn, vals=vals)
+                   fmod, fpfn, vals=vals, single_op=single_op)
 
 
-def runfp(dut, width, name, fpkls, fpop, single_op=False, n_vals=10, vals=None):
+def runfp(dut, width, name, fpkls, fpop, single_op=False, n_vals=10,
+          vals=None, opcode=None):
     vl = rtlil.convert(dut, ports=dut.ports())
     with open("%s.il" % name, "w") as f:
         f.write(vl)
@@ -178,7 +202,7 @@ def runfp(dut, width, name, fpkls, fpop, single_op=False, n_vals=10, vals=None):
     if vals is None:
         vals = create_random(dut.num_rows, width, single_op, n_vals)
 
-    test = MuxInOut(dut, width, fpkls, fpop, vals, single_op)
+    test = MuxInOut(dut, width, fpkls, fpop, vals, single_op, opcode=opcode)
     fns = []
     for i in range(dut.num_rows):
         fns.append(test.rcv(i))