add single op fcvt test case

[ieee754fpu.git] / src / ieee754 / fpcommon / test / unit_test_half.py

diff --git a/src/ieee754/fpcommon/test/unit_test_half.py b/src/ieee754/fpcommon/test/unit_test_half.py
index 50c9c24e021d8ae5d0f046bd3a1f835dafde8a42..a0a35cb2eba9ae7bab5d915ea68e11ce828b119f 100644 (file)
--- a/src/ieee754/fpcommon/test/unit_test_half.py
+++ b/src/ieee754/fpcommon/test/unit_test_half.py
@@ -4,11 +4,16 @@ from random import seed
 import sys
 from sfpy import Float16
 
+max_e = 16
+
 def get_mantissa(x):
     return 0x3ff & x
 
 def get_exponent(x):
-    return ((x & 0xf800) >> 11) - 15
+    return ((x & 0x7800) >> 11) - 15
+
+def set_exponent(x, e):
+    return (x & ~0x7800) | ((e+15) << 11)
 
 def get_sign(x):
     return ((x & 0x8000) >> 15)
@@ -33,6 +38,18 @@ def match(x, y):
         (x == y)
         )
 
+def create(s, e, m):
+    return set_exponent((s<<15) | m, e)
+
+def inf(s):
+    return create(s, 16, 0)
+
+def nan(s):
+    return create(s, 16, 1<<10)
+
+def zero(s):
+    return s<<15
+
 def get_case(dut, a, b):
     yield dut.in_a.v.eq(a)
     yield dut.in_a.stb.eq(1)