fix shifting of rsqrt mantissa input

[ieee754fpu.git] / src / ieee754 / fpdiv / div0.py

diff --git a/src/ieee754/fpdiv/div0.py b/src/ieee754/fpdiv/div0.py
index 0c9ed334adc6b8a913a8e3f2de08e74d69182399..c93ba723a0d303443a9ad0b78612945e283bc3f4 100644 (file)
--- a/src/ieee754/fpdiv/div0.py
+++ b/src/ieee754/fpdiv/div0.py
@@ -121,8 +121,8 @@ class FPDivStage0Mod(Elaboratable):
                     m.d.comb += am0.eq(Cat(self.i.a.m, 0)<<(extra-3))
                     m.d.comb += self.o.z.e.eq(-((self.i.a.e+1) >> 1)+4)
                 with m.Else():
-                    m.d.comb += am0.eq(Cat(0, self.i.a.m)<<(extra-3))
-                    m.d.comb += self.o.z.e.eq((self.i.a.e >> 1)+2)
+                    m.d.comb += am0.eq(Cat(self.i.a.m)<<(extra-2))
+                    m.d.comb += self.o.z.e.eq(-(self.i.a.e >> 1)+4)
 
                 m.d.comb += [self.o.z.s.eq(self.i.a.s),
                              self.o.divisor_radicand.eq(am0),