-"""IEEE754 Floating Point Divider
+"""IEEE754 Floating Point Divider
+
+Copyright (C) 2019 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Copyright (C) 2019 Jacob Lifshay
+
+Relevant bugreports:
+* http://bugs.libre-riscv.org/show_bug.cgi?id=99
+* http://bugs.libre-riscv.org/show_bug.cgi?id=43
+* http://bugs.libre-riscv.org/show_bug.cgi?id=44
-Relevant bugreport: http://bugs.libre-riscv.org/show_bug.cgi?id=99
"""
-from nmigen import Module, Signal, Cat, Elaboratable
+from nmigen import Module, Signal, Cat, Elaboratable, Const, Mux
from nmigen.cli import main, verilog
-from ieee754.fpcommon.fpbase import (FPNumBaseRecord, Overflow)
-from ieee754.fpcommon.fpbase import FPState
+from nmutil.pipemodbase import PipeModBase
+from ieee754.fpcommon.fpbase import FPNumBaseRecord
from ieee754.fpcommon.denorm import FPSCData
from ieee754.fpcommon.getop import FPPipeContext
+from ieee754.div_rem_sqrt_rsqrt.div_pipe import DivPipeInputData
+from ieee754.div_rem_sqrt_rsqrt.core import DivPipeCoreOperation as DPCOp
-class FPDivStage0Data:
+class FPDivPreFPAdjust(PipeModBase):
+ """ DIV/SQRT/RSQRT "preparation" module.
- def __init__(self, width, pspec):
- self.z = FPNumBaseRecord(width, False)
- self.out_do_z = Signal(reset_less=True)
- self.oz = Signal(width, reset_less=True)
- self.of = Overflow()
+ adjusts mantissa and exponent (sqrt/rsqrt exponent must be even),
+ puts exponent (and sign) into data structures for passing through to
+ the end, and puts the (adjusted) mantissa into the processing engine.
- self.ctx = FPPipeContext(width, pspec) # context: muxid, operator etc.
- self.muxid = self.ctx.muxid # annoying. complicated.
+ no *actual* processing occurs here: it is *purely* preparation work.
+ """
+ def __init__(self, pspec):
+ super().__init__(pspec, "pre_fp_adjust")
- # TODO: here is where Q and R would be put, and passed
- # down to Stage1 processing.
+ def ispec(self):
+ return FPSCData(self.pspec, False)
- mw = (self.z.m_width)*2 - 1 + 3 # sticky/round/guard bits + (2*mant) - 1
- self.product = Signal(mw, reset_less=True)
+ def ospec(self):
+ return DivPipeInputData(self.pspec)
- def eq(self, i):
- return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
- self.of.eq(i.of),
- self.product.eq(i.product), self.ctx.eq(i.ctx)]
+ def elaborate(self, platform):
+ m = Module()
+ comb = m.d.comb
+ # mantissas start in the range [1.0, 2.0)
-class FPDivStage0Mod(Elaboratable):
+ # intermediary temp signals
+ is_div = Signal(reset_less=True)
+ need_exp_adj = Signal(reset_less=True)
- def __init__(self, width, id_wid):
- self.width = width
- self.id_wid = id_wid
- self.i = self.ispec()
- self.o = self.ospec()
+ # "adjusted" - ``self.i.a.rmw`` fractional bits and 2 integer bits
+ adj_a_mw = self.i.a.rmw
+ adj_a_m = Signal(self.i.a.rmw + 2, reset_less=True)
+ adj_a_e = Signal((len(self.i.a.e), True), reset_less=True)
- def ispec(self):
- return FPSCData(self.width, self.id_wid, False)
+ # adjust (shift) the exponent so that it is even, but only for [r]sqrt
+ comb += [is_div.eq(self.i.ctx.op == int(DPCOp.UDivRem)),
+ need_exp_adj.eq(~is_div & self.i.a.e[0]), # even? !div? adjust
+ adj_a_m.eq(self.i.a.m << need_exp_adj),
+ adj_a_e.eq(self.i.a.e - need_exp_adj)]
- def ospec(self):
- return FPDivStage0Data(self.width, self.id_wid)
+ # adj_a_m now in the range [1.0, 4.0) for sqrt/rsqrt
+ # and [1.0, 2.0) for div
- def process(self, i):
- return self.o
+ fw = self.pspec.core_config.fract_width
+ divr_rad = Signal(len(self.o.divisor_radicand), reset_less=True)
- def setup(self, m, i):
- """ links module to inputs and outputs
- """
- m.submodules.div0 = self
- m.d.comb += self.i.eq(i)
+ # real mantissa fractional widths
+ a_mw = self.i.a.rmw
+ b_mw = self.i.b.rmw
- def elaborate(self, platform):
- m = Module()
+ comb += [self.o.dividend.eq(self.i.a.m << (fw*2 - a_mw)),
+ divr_rad.eq(Mux(is_div, self.i.b.m << (fw - b_mw),
+ adj_a_m << (fw - adj_a_mw))),
+ self.o.divisor_radicand.eq(divr_rad),
+ ]
- # XXX TODO, actual DIV code here. this class would be
- # "step one" which takes the pre-normalised data (see ispec) and
- # *begins* the processing phase (enters the massive DIV
- # pipeline chain) - see ospec.
-
- # NOTE: this stage does *NOT* do *ACTUAL* DIV processing,
- # it is PURELY the *ENTRY* point into the chain, performing
- # "preparation" work
-
- # store intermediate tests (and zero-extended mantissas)
- am0 = Signal(len(self.i.a.m)+1, reset_less=True)
- bm0 = Signal(len(self.i.b.m)+1, reset_less=True)
- m.d.comb += [
- am0.eq(Cat(self.i.a.m, 0)),
- bm0.eq(Cat(self.i.b.m, 0))
- ]
- # same-sign (both negative or both positive) div mantissas
with m.If(~self.i.out_do_z):
- m.d.comb += [self.o.z.e.eq(self.i.a.e + self.i.b.e + 1),
- # TODO: no, not product, first stage Q and R etc. etc.
- # go here.
- self.o.product.eq(am0 * bm0 * 4),
- self.o.z.s.eq(self.i.a.s ^ self.i.b.s)
- ]
-
- m.d.comb += self.o.oz.eq(self.i.oz)
- m.d.comb += self.o.out_do_z.eq(self.i.out_do_z)
- m.d.comb += self.o.ctx.eq(self.i.ctx)
- return m
-
+ # DIV
+ with m.If(self.i.ctx.op == int(DPCOp.UDivRem)):
+ # DIV: subtract exponents, XOR sign
+ comb += [self.o.z.e.eq(self.i.a.e - self.i.b.e),
+ self.o.z.s.eq(self.i.a.s ^ self.i.b.s),
+ self.o.operation.eq(int(DPCOp.UDivRem))
+ ]
+ # SQRT
+ with m.Elif(self.i.ctx.op == int(DPCOp.SqrtRem)):
+ # SQRT: sign is the same, [adjusted] exponent is halved
+ comb += [self.o.z.e.eq(adj_a_e >> 1), # halve
+ self.o.z.s.eq(self.i.a.s),
+ self.o.operation.eq(int(DPCOp.SqrtRem))
+ ]
+ # RSQRT
+ with m.Elif(self.i.ctx.op == int(DPCOp.RSqrtRem)):
+ # RSQRT: sign same, [adjusted] exponent halved and inverted
+ comb += [self.o.z.e.eq(-(adj_a_e >> 1)), # NEGATE and halve
+ self.o.z.s.eq(self.i.a.s),
+ self.o.operation.eq(int(DPCOp.RSqrtRem))
+ ]
+
+ # these are required and must not be touched
+ comb += self.o.oz.eq(self.i.oz)
+ comb += self.o.out_do_z.eq(self.i.out_do_z)
+ comb += self.o.ctx.eq(self.i.ctx)
-class FPDivStage0(FPState):
- """ First stage of div.
- """
-
- def __init__(self, width, id_wid):
- FPState.__init__(self, "divider_0")
- self.mod = FPDivStage0Mod(width)
- self.o = self.mod.ospec()
-
- def setup(self, m, i):
- """ links module to inputs and outputs
- """
- self.mod.setup(m, i)
+ return m
- # NOTE: these could be done as combinatorial (merge div0+div1)
- m.d.sync += self.o.eq(self.mod.o)
- def action(self, m):
- m.next = "divider_1"
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