start adding use of DivPipeInputData and DivPipeInterstageData

[ieee754fpu.git] / src / ieee754 / fpdiv / div0.py

diff --git a/src/ieee754/fpdiv/div0.py b/src/ieee754/fpdiv/div0.py
index 167edde662eda12b7b774474ba09359b039c5ec3..30d92c6d0854f09d308a72ee7ea8709dd4d079ad 100644 (file)
--- a/src/ieee754/fpdiv/div0.py
+++ b/src/ieee754/fpdiv/div0.py
@@ -9,15 +9,20 @@ from nmigen.cli import main, verilog
 from ieee754.fpcommon.fpbase import (FPNumBaseRecord, Overflow)
 from ieee754.fpcommon.fpbase import FPState
 from ieee754.fpcommon.denorm import FPSCData
+from ieee754.fpcommon.getop import FPPipeContext
+from ieee754.div_rem_sqrt_rsqrt.div_pipe import DivPipeInputData
 
 
+# TODO: delete (replace by DivPipeCoreInputData)
 class FPDivStage0Data:
 
-    def __init__(self, width, id_wid):
-        self.z = FPNumBaseRecord(width, False)
+    def __init__(self, pspec):
+        self.z = FPNumBaseRecord(pspec.width, False)
         self.out_do_z = Signal(reset_less=True)
-        self.oz = Signal(width, reset_less=True)
-        self.of = Overflow()
+        self.oz = Signal(pspec.width, reset_less=True)
+
+        self.ctx = FPPipeContext(pspec.width, pspec) # context: muxid, operator etc.
+        self.muxid = self.ctx.muxid             # annoying. complicated.
 
         # TODO: here is where Q and R would be put, and passed
         # down to Stage1 processing.
@@ -25,27 +30,23 @@ class FPDivStage0Data:
         mw = (self.z.m_width)*2 - 1 + 3 # sticky/round/guard bits + (2*mant) - 1
         self.product = Signal(mw, reset_less=True)
 
-        self.mid = Signal(id_wid, reset_less=True)
-
     def eq(self, i):
         return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
-                self.of.eq(i.of),
-                self.product.eq(i.product), self.mid.eq(i.mid)]
+                self.product.eq(i.product), self.ctx.eq(i.ctx)]
 
 
 class FPDivStage0Mod(Elaboratable):
 
-    def __init__(self, width, id_wid):
-        self.width = width
-        self.id_wid = id_wid
+    def __init__(self, pspec):
+        self.pspec = pspec
         self.i = self.ispec()
         self.o = self.ospec()
 
     def ispec(self):
-        return FPSCData(self.width, self.id_wid, False)
+        return FPSCData(self.pspec, False)
 
     def ospec(self):
-        return FPDivStage0Data(self.width, self.id_wid)
+        return DivPipeInputData(self.pspec)
 
     def process(self, i):
         return self.o
@@ -64,25 +65,29 @@ class FPDivStage0Mod(Elaboratable):
         # *begins* the processing phase (enters the massive DIV
         # pipeline chain) - see ospec.
 
-        # store intermediate tests (and zero-extended mantissas)
-        am0 = Signal(len(self.i.a.m)+1, reset_less=True)
-        bm0 = Signal(len(self.i.b.m)+1, reset_less=True)
-        m.d.comb += [
-                     am0.eq(Cat(self.i.a.m, 0)),
-                     bm0.eq(Cat(self.i.b.m, 0))
-                    ]
-        # same-sign (both negative or both positive) div mantissas
+        # INPUT SPEC: FPSCData
+        # OUTPUT SPEC: DivPipeCoreInputData
+
+        # NOTE: this stage does *NOT* do *ACTUAL* DIV processing,
+        # it is PURELY the *ENTRY* point into the chain, performing
+        # "preparation" work.
+
         with m.If(~self.i.out_do_z):
-            m.d.comb += [self.o.z.e.eq(self.i.a.e + self.i.b.e + 1),
-                         # TODO: no, not product, first stage Q and R etc. etc.
-                         # go here.
-                         self.o.product.eq(am0 * bm0 * 4),
+            # do conversion here, of both self.i.a and self.i.b,
+            # into DivPipeCoreInputData dividend and divisor.
+
+            m.d.comb += [self.o.z.e.eq(self.i.a.e - self.i.b.e + 1),
                          self.o.z.s.eq(self.i.a.s ^ self.i.b.s)
+                         self.o.dividend.eq(self.i.a.m), # TODO: check
+                         self.o.divisor_radicand.eq(self.i.b.m), # TODO: check
+                         self.o.operation.eq(Const(0)) # TODO (set from ctx.op)
                 ]
 
+        # these are required and must not be touched
         m.d.comb += self.o.oz.eq(self.i.oz)
         m.d.comb += self.o.out_do_z.eq(self.i.out_do_z)
-        m.d.comb += self.o.mid.eq(self.i.mid)
+        m.d.comb += self.o.ctx.eq(self.i.ctx)
+
         return m
 
 
@@ -90,9 +95,9 @@ class FPDivStage0(FPState):
     """ First stage of div.  
     """
 
-    def __init__(self, width, id_wid):
+    def __init__(self, pspec):
         FPState.__init__(self, "divider_0")
-        self.mod = FPDivStage0Mod(width)
+        self.mod = FPDivStage0Mod(pspec)
         self.o = self.mod.ospec()
 
     def setup(self, m, i):