Relevant bugreport: http://bugs.libre-riscv.org/show_bug.cgi?id=99
"""
-from nmigen import Module, Signal, Cat, Elaboratable
+from nmigen import Module, Signal, Cat, Elaboratable, Const
from nmigen.cli import main, verilog
from ieee754.fpcommon.fpbase import (FPNumBaseRecord, Overflow)
from ieee754.div_rem_sqrt_rsqrt.div_pipe import DivPipeInputData
-# TODO: delete (replace by DivPipeCoreInputData)
-class FPDivStage0Data:
-
- def __init__(self, pspec):
- self.z = FPNumBaseRecord(pspec.width, False)
- self.out_do_z = Signal(reset_less=True)
- self.oz = Signal(pspec.width, reset_less=True)
-
- self.ctx = FPPipeContext(pspec.width, pspec) # context: muxid, operator etc.
- self.muxid = self.ctx.muxid # annoying. complicated.
-
- # TODO: here is where Q and R would be put, and passed
- # down to Stage1 processing.
-
- mw = (self.z.m_width)*2 - 1 + 3 # sticky/round/guard bits + (2*mant) - 1
- self.product = Signal(mw, reset_less=True)
-
- def eq(self, i):
- return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
- self.product.eq(i.product), self.ctx.eq(i.ctx)]
-
-
class FPDivStage0Mod(Elaboratable):
def __init__(self, pspec):
# pipeline chain) - see ospec.
# INPUT SPEC: FPSCData
- # OUTPUT SPEC: DivPipeCoreInputData
+ # OUTPUT SPEC: DivPipeInputData
# NOTE: this stage does *NOT* do *ACTUAL* DIV processing,
# it is PURELY the *ENTRY* point into the chain, performing
with m.If(~self.i.out_do_z):
# do conversion here, of both self.i.a and self.i.b,
- # into DivPipeCoreInputData dividend and divisor.
+ # into DivPipeInputData dividend and divisor.
+
+ # XXX *sigh* magic constants...
+ if self.pspec.width == 16:
+ if self.pspec.log2_radix == 1:
+ extra = 2
+ elif self.pspec.log2_radix == 3:
+ extra = 2
+ else:
+ extra = 3
+ elif self.pspec.width == 32:
+ if self.pspec.log2_radix == 1:
+ extra = 3
+ else:
+ extra = 4
+ elif self.pspec.width == 64:
+ if self.pspec.log2_radix == 1:
+ extra = 2
+ elif self.pspec.log2_radix == 3:
+ extra = 2
+ else:
+ extra = 3
# the mantissas, having been de-normalised (and containing
# a "1" in the MSB) represent numbers in the range 0.5 to
# result is therefore 0.4999999 (0.5/0.99999) and 1.9999998
# (0.99999/0.5).
- # zero-extend the mantissas (room for sticky/guard)
- # plus the extra MSB. See DivPipeBaseStage.get_core_config
- am0 = Signal(len(self.i.a.m)+3, reset_less=True)
- bm0 = Signal(len(self.i.b.m)+3, reset_less=True)
- m.d.comb += [
- am0.eq(Cat(0, 0, self.i.a.m, 0)),
- bm0.eq(Cat(0, 0, self.i.b.m, 0))
- ]
-
- m.d.comb += [self.o.z.e.eq(self.i.a.e - self.i.b.e + 1),
- self.o.z.s.eq(self.i.a.s ^ self.i.b.s)
- self.o.dividend.eq(am0), # TODO: check
- self.o.divisor_radicand.eq(bm0), # TODO: check
- self.o.operation.eq(Const(0)) # TODO check: DIV
- ]
+ # DIV
+ with m.If(self.i.ctx.op == 0):
+ am0 = Signal(len(self.i.a.m)+3, reset_less=True)
+ bm0 = Signal(len(self.i.b.m)+3, reset_less=True)
+ m.d.comb += [
+ am0.eq(Cat(0,0,0,self.i.a.m, 0)),
+ bm0.eq(Cat(0,0,0,self.i.b.m, 0)),
+ ]
+
+ # zero-extend the mantissas (room for sticky/round/guard)
+ # plus the extra MSB.
+ m.d.comb += [self.o.z.e.eq(self.i.a.e - self.i.b.e + 1),
+ self.o.z.s.eq(self.i.a.s ^ self.i.b.s),
+ self.o.dividend[len(self.i.a.m)+extra:].eq(am0),
+ self.o.divisor_radicand.eq(bm0),
+ self.o.operation.eq(Const(0)) # XXX DIV operation
+ ]
+
+ # SQRT
+ with m.Elif(self.i.ctx.op == 1):
+ am0 = Signal(len(self.i.a.m)+3, reset_less=True)
+ with m.If(self.i.a.e[0]):
+ m.d.comb += am0.eq(Cat(self.i.a.m, 0)<<(extra-2))
+ m.d.comb += self.o.z.e.eq(((self.i.a.e+1) >> 1)+1)
+ with m.Else():
+ m.d.comb += am0.eq(Cat(0, self.i.a.m)<<(extra-2))
+ m.d.comb += self.o.z.e.eq((self.i.a.e >> 1)+1)
+
+ m.d.comb += [self.o.z.s.eq(self.i.a.s),
+ self.o.divisor_radicand.eq(am0),
+ self.o.operation.eq(Const(1)) # XXX SQRT operation
+ ]
# these are required and must not be touched
m.d.comb += self.o.oz.eq(self.i.oz)
projects / ieee754fpu.git / blobdiff