-"""IEEE754 Floating Point Divider
+"""IEEE754 Floating Point Divider
Relevant bugreport: http://bugs.libre-riscv.org/show_bug.cgi?id=99
"""
-from nmigen import Module, Signal, Cat, Elaboratable
+from nmigen import Module, Signal, Cat, Elaboratable, Const
from nmigen.cli import main, verilog
from ieee754.fpcommon.fpbase import (FPNumBaseRecord, Overflow)
from ieee754.fpcommon.fpbase import FPState
from ieee754.fpcommon.denorm import FPSCData
-
-
-class FPDivStage0Data:
-
- def __init__(self, width, id_wid):
- self.z = FPNumBaseRecord(width, False)
- self.out_do_z = Signal(reset_less=True)
- self.oz = Signal(width, reset_less=True)
- self.of = Overflow()
-
- # TODO: here is where Q and R would be put, and passed
- # down to Stage1 processing.
-
- mw = (self.z.m_width)*2 - 1 + 3 # sticky/round/guard bits + (2*mant) - 1
- self.product = Signal(mw, reset_less=True)
-
- self.mid = Signal(id_wid, reset_less=True)
-
- def eq(self, i):
- return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
- self.of.eq(i.of),
- self.product.eq(i.product), self.mid.eq(i.mid)]
+from ieee754.fpcommon.getop import FPPipeContext
+from ieee754.div_rem_sqrt_rsqrt.div_pipe import DivPipeInputData
class FPDivStage0Mod(Elaboratable):
- def __init__(self, width, id_wid):
- self.width = width
- self.id_wid = id_wid
+ def __init__(self, pspec):
+ self.pspec = pspec
self.i = self.ispec()
self.o = self.ospec()
def ispec(self):
- return FPSCData(self.width, self.id_wid, False)
+ return FPSCData(self.pspec, False)
def ospec(self):
- return FPDivStage0Data(self.width, self.id_wid)
+ return DivPipeInputData(self.pspec)
def process(self, i):
return self.o
# *begins* the processing phase (enters the massive DIV
# pipeline chain) - see ospec.
- # store intermediate tests (and zero-extended mantissas)
- am0 = Signal(len(self.i.a.m)+1, reset_less=True)
- bm0 = Signal(len(self.i.b.m)+1, reset_less=True)
- m.d.comb += [
- am0.eq(Cat(self.i.a.m, 0)),
- bm0.eq(Cat(self.i.b.m, 0))
- ]
- # same-sign (both negative or both positive) div mantissas
+ # INPUT SPEC: FPSCData
+ # OUTPUT SPEC: DivPipeInputData
+
+ # NOTE: this stage does *NOT* do *ACTUAL* DIV processing,
+ # it is PURELY the *ENTRY* point into the chain, performing
+ # "preparation" work.
+
with m.If(~self.i.out_do_z):
- m.d.comb += [self.o.z.e.eq(self.i.a.e + self.i.b.e + 1),
- # TODO: no, not product, first stage Q and R etc. etc.
- # go here.
- self.o.product.eq(am0 * bm0 * 4),
- self.o.z.s.eq(self.i.a.s ^ self.i.b.s)
+ # do conversion here, of both self.i.a and self.i.b,
+ # into DivPipeInputData dividend and divisor.
+
+ # XXX *sigh* magic constants...
+ if self.pspec.width == 16:
+ if self.pspec.log2_radix == 1:
+ extra = 2
+ elif self.pspec.log2_radix == 3:
+ extra = 2
+ else:
+ extra = 3
+ elif self.pspec.width == 32:
+ if self.pspec.log2_radix == 1:
+ extra = 3
+ else:
+ extra = 4
+ elif self.pspec.width == 64:
+ if self.pspec.log2_radix == 1:
+ extra = 2
+ elif self.pspec.log2_radix == 3:
+ extra = 2
+ else:
+ extra = 3
+ # the mantissas, having been de-normalised (and containing
+ # a "1" in the MSB) represent numbers in the range 0.5 to
+ # 0.9999999-recurring. the min and max range of the
+ # result is therefore 0.4999999 (0.5/0.99999) and 1.9999998
+ # (0.99999/0.5).
+
+ # zero-extend the mantissas (room for sticky/guard)
+ # plus the extra MSB. See DivPipeBaseStage.get_core_config
+ am0 = Signal(len(self.i.a.m)+3, reset_less=True)
+ bm0 = Signal(len(self.i.b.m)+3, reset_less=True)
+ m.d.comb += [
+ am0.eq(Cat(0,0,0,self.i.a.m, 0)),
+ bm0.eq(Cat(0,0,0,self.i.b.m, 0)),
+ #am0.eq(0x392),
+ #bm0.eq(0x1110),
+ ]
+
+ m.d.comb += [self.o.z.e.eq(self.i.a.e - self.i.b.e + 1),
+ self.o.z.s.eq(self.i.a.s ^ self.i.b.s),
+ self.o.dividend[len(self.i.a.m)+extra:].eq(am0), # TODO: check
+ self.o.divisor_radicand.eq(bm0), # TODO: check
+ self.o.operation.eq(Const(0)) # TODO check: DIV
]
+ # these are required and must not be touched
m.d.comb += self.o.oz.eq(self.i.oz)
m.d.comb += self.o.out_do_z.eq(self.i.out_do_z)
- m.d.comb += self.o.mid.eq(self.i.mid)
+ m.d.comb += self.o.ctx.eq(self.i.ctx)
+
return m
class FPDivStage0(FPState):
- """ First stage of div.
+ """ First stage of div.
"""
- def __init__(self, width, id_wid):
+ def __init__(self, pspec):
FPState.__init__(self, "divider_0")
- self.mod = FPDivStage0Mod(width)
+ self.mod = FPDivStage0Mod(pspec)
self.o = self.mod.ospec()
def setup(self, m, i):
projects / ieee754fpu.git / blobdiff