fix imports

[ieee754fpu.git] / src / ieee754 / fpdiv / div0.py

diff --git a/src/ieee754/fpdiv/div0.py b/src/ieee754/fpdiv/div0.py
index c6e74ecf9476ec5b443c0ebdadd8d29541819885..35cc41aaef42e1e1607d632eb9f71fd25b0b2a34 100644 (file)
--- a/src/ieee754/fpdiv/div0.py
+++ b/src/ieee754/fpdiv/div0.py
@@ -1,4 +1,4 @@
-"""IEEE754 Floating Point Divider 
+"""IEEE754 Floating Point Divider
 
 Relevant bugreport: http://bugs.libre-riscv.org/show_bug.cgi?id=99
 """
@@ -46,8 +46,7 @@ class FPDivStage0Mod(Elaboratable):
         return FPSCData(self.pspec, False)
 
     def ospec(self):
-        # XXX TODO: replace with DivPipeCoreInputData, here
-        return FPDivStage0Data(self.pspec)
+        return DivPipeInputData(self.pspec)
 
     def process(self, i):
         return self.o
@@ -77,11 +76,26 @@ class FPDivStage0Mod(Elaboratable):
             # do conversion here, of both self.i.a and self.i.b,
             # into DivPipeCoreInputData dividend and divisor.
 
+            # the mantissas, having been de-normalised (and containing
+            # a "1" in the MSB) represent numbers in the range 0.5 to
+            # 0.9999999-recurring.  the min and max range of the
+            # result is therefore 0.4999999 (0.5/0.99999) and 1.9999998
+            # (0.99999/0.5).
+
+            # zero-extend the mantissas (room for sticky/guard)
+            # plus the extra MSB.  See DivPipeBaseStage.get_core_config
+            am0 = Signal(len(self.i.a.m)+3, reset_less=True)
+            bm0 = Signal(len(self.i.b.m)+3, reset_less=True)
+            m.d.comb += [
+                         am0.eq(Cat(0, 0, self.i.a.m, 0)),
+                         bm0.eq(Cat(0, 0, self.i.b.m, 0))
+                        ]
+
             m.d.comb += [self.o.z.e.eq(self.i.a.e - self.i.b.e + 1),
-                         self.o.z.s.eq(self.i.a.s ^ self.i.b.s)
-                         self.o.dividend.eq(self.i.a.m), # TODO: check
-                         self.o.divisor_radicand.eq(self.i.b.m), # TODO: check
-                         self.o.operation.eq(Const(0)) # TODO (set from ctx.op)
+                         self.o.z.s.eq(self.i.a.s ^ self.i.b.s),
+                         self.o.dividend.eq(am0), # TODO: check
+                         self.o.divisor_radicand.eq(bm0), # TODO: check
+                         self.o.operation.eq(Const(0)) # TODO check: DIV
                 ]
 
         # these are required and must not be touched
@@ -93,7 +107,7 @@ class FPDivStage0Mod(Elaboratable):
 
 
 class FPDivStage0(FPState):
-    """ First stage of div.  
+    """ First stage of div.
     """
 
     def __init__(self, pspec):