Relevant bugreport: http://bugs.libre-riscv.org/show_bug.cgi?id=99
"""
-from nmigen import Module, Signal, Cat, Elaboratable
+from nmigen import Module, Signal, Cat, Elaboratable, Const
from nmigen.cli import main, verilog
from ieee754.fpcommon.fpbase import (FPNumBaseRecord, Overflow)
# do conversion here, of both self.i.a and self.i.b,
# into DivPipeInputData dividend and divisor.
+ if self.pspec.width == 16:
+ extra = 3
+ elif self.pspec.width == 32:
+ extra = 4
+ elif self.pspec.width == 64:
+ extra = 3
# the mantissas, having been de-normalised (and containing
# a "1" in the MSB) represent numbers in the range 0.5 to
# 0.9999999-recurring. the min and max range of the
am0 = Signal(len(self.i.a.m)+3, reset_less=True)
bm0 = Signal(len(self.i.b.m)+3, reset_less=True)
m.d.comb += [
- am0.eq(Cat(0, 0, self.i.a.m, 0)),
- bm0.eq(Cat(0, 0, self.i.b.m, 0))
+ am0.eq(Cat(0,0,0,self.i.a.m, 0)),
+ bm0.eq(Cat(0,0,0,self.i.b.m, 0)),
+ #am0.eq(0x392),
+ #bm0.eq(0x1110),
]
m.d.comb += [self.o.z.e.eq(self.i.a.e - self.i.b.e + 1),
self.o.z.s.eq(self.i.a.s ^ self.i.b.s),
- self.o.dividend.eq(am0), # TODO: check
+ self.o.dividend[len(self.i.a.m)+extra:].eq(am0), # TODO: check
self.o.divisor_radicand.eq(bm0), # TODO: check
self.o.operation.eq(Const(0)) # TODO check: DIV
]