split out adder code (PartitionedAdder) into module, PartitionPoints too

[ieee754fpu.git] / src / ieee754 / fpdiv / div0.py

diff --git a/src/ieee754/fpdiv/div0.py b/src/ieee754/fpdiv/div0.py
index 37583b0f289e049267aed53f1d393a95f6662a0e..971224bef2bc94558aeac7a5eaabdd01494d83a9 100644 (file)
--- a/src/ieee754/fpdiv/div0.py
+++ b/src/ieee754/fpdiv/div0.py
@@ -1,4 +1,4 @@
-"""IEEE754 Floating Point Divider
+"""IEEE754 Floating Point Divider / Square-Root / Reciprocal-Square-Root
 
 Copyright (C) 2019 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 Copyright (C) 2019 Jacob Lifshay
@@ -21,7 +21,7 @@ from ieee754.div_rem_sqrt_rsqrt.div_pipe import DivPipeInputData
 from ieee754.div_rem_sqrt_rsqrt.core import DivPipeCoreOperation as DPCOp
 
 
-class FPDivStage0Mod(PipeModBase):
+class FPDivPreFPAdjust(PipeModBase):
     """ DIV/SQRT/RSQRT "preparation" module.
 
     adjusts mantissa and exponent (sqrt/rsqrt exponent must be even),
@@ -31,7 +31,7 @@ class FPDivStage0Mod(PipeModBase):
     no *actual* processing occurs here: it is *purely* preparation work.
     """
     def __init__(self, pspec):
-        super().__init__(pspec, "div0")
+        super().__init__(pspec, "pre_fp_adjust")
 
     def ispec(self):
         return FPSCData(self.pspec, False)
@@ -76,30 +76,31 @@ class FPDivStage0Mod(PipeModBase):
                  self.o.divisor_radicand.eq(divr_rad),
         ]
 
-        with m.If(~self.i.out_do_z):
-            # DIV
-            with m.If(self.i.ctx.op == int(DPCOp.UDivRem)):
-                # DIV: subtract exponents, XOR sign
-                comb += [self.o.z.e.eq(self.i.a.e - self.i.b.e),
-                         self.o.z.s.eq(self.i.a.s ^ self.i.b.s),
-                         self.o.operation.eq(int(DPCOp.UDivRem))
-                        ]
-            # SQRT
-            with m.Elif(self.i.ctx.op == int(DPCOp.SqrtRem)):
-                # SQRT: sign is the same, [adjusted] exponent is halved
-                comb += [self.o.z.e.eq(adj_a_e >> 1), # halve
-                         self.o.z.s.eq(self.i.a.s),
-                         self.o.operation.eq(int(DPCOp.SqrtRem))
-                        ]
-            # RSQRT
-            with m.Elif(self.i.ctx.op == int(DPCOp.RSqrtRem)):
-                # RSQRT: sign same, [adjusted] exponent halved and inverted
-                comb += [self.o.z.e.eq(-(adj_a_e >> 1)), # NEGATE and halve
-                         self.o.z.s.eq(self.i.a.s),
-                         self.o.operation.eq(int(DPCOp.RSqrtRem))
-                        ]
-
-        # these are required and must not be touched
+        ############# DIV #############
+        with m.If(self.i.ctx.op == int(DPCOp.UDivRem)):
+            # DIV: subtract exponents, XOR sign
+            comb += [self.o.z.e.eq(self.i.a.e - self.i.b.e),
+                     self.o.z.s.eq(self.i.a.s ^ self.i.b.s),
+                     self.o.operation.eq(int(DPCOp.UDivRem))
+                    ]
+
+        ############# SQRT #############
+        with m.Elif(self.i.ctx.op == int(DPCOp.SqrtRem)):
+            # SQRT: sign is the same, [adjusted] exponent is halved
+            comb += [self.o.z.e.eq(adj_a_e >> 1), # halve
+                     self.o.z.s.eq(self.i.a.s),
+                     self.o.operation.eq(int(DPCOp.SqrtRem))
+                    ]
+
+        ############# RSQRT #############
+        with m.Elif(self.i.ctx.op == int(DPCOp.RSqrtRem)):
+            # RSQRT: sign same, [adjusted] exponent halved and inverted
+            comb += [self.o.z.e.eq(-(adj_a_e >> 1)), # NEGATE and halve
+                     self.o.z.s.eq(self.i.a.s),
+                     self.o.operation.eq(int(DPCOp.RSqrtRem))
+                    ]
+
+        # pass through context
         comb += self.o.oz.eq(self.i.oz)
         comb += self.o.out_do_z.eq(self.i.out_do_z)
         comb += self.o.ctx.eq(self.i.ctx)