big (single-purpose) update: move width arg into pspec

[ieee754fpu.git] / src / ieee754 / fpdiv / div1.py

diff --git a/src/ieee754/fpdiv/div1.py b/src/ieee754/fpdiv/div1.py
index 52edde60fb364b40f48a40a448d71bf6013a4e7f..6cf49aba062b9ee73e8587c8f3d622ed83be09a7 100644 (file)
--- a/src/ieee754/fpdiv/div1.py
+++ b/src/ieee754/fpdiv/div1.py
@@ -1,4 +1,4 @@
-"""IEEE754 Floating Point Divider 
+"""IEEE754 Floating Point Divider
 
 Relevant bugreport: http://bugs.libre-riscv.org/show_bug.cgi?id=99
 """
@@ -9,22 +9,23 @@ from nmigen.cli import main, verilog
 from ieee754.fpcommon.fpbase import FPNumBaseRecord
 from ieee754.fpcommon.fpbase import FPState
 from ieee754.fpcommon.denorm import FPSCData
-from .div0 import FPDivStage0Data
+from .div0 import FPDivStage0Data # TODO: replace with DivPipeCoreInterstageData
 
 
 class FPDivStage1Mod(Elaboratable):
 
-    def __init__(self, width, id_wid):
-        self.width = width
-        self.id_wid = id_wid
+    def __init__(self, pspec):
+        self.pspec = pspec
         self.i = self.ispec()
         self.o = self.ospec()
 
     def ispec(self):
-        return FPDivStage0Data(self.width, self.id_wid)
+        # TODO: DivPipeCoreInterstageData, here
+        return FPDivStage0Data(self.pspec) # Q/Rem (etc) in...
 
     def ospec(self):
-        return FPDivStage0Data(self.width, self.id_wid)
+        # TODO: DivPipeCoreInterstageData, here
+        return FPDivStage0Data(self.pspec) # ... Q/Rem (etc) out
 
     def process(self, i):
         return self.o
@@ -39,8 +40,12 @@ class FPDivStage1Mod(Elaboratable):
         m = Module()
 
         # XXX TODO, actual DIV code here.  this class would be
-        # "step two" and is the main "chain".  tons of these needed.
-        # here is where Q and R are used, TODO: those are in FPDivStage0Data.
+        # here is where Q and R are used, TODO: Q/REM (etc) need to be in
+        # FPDivStage0Data.
+
+        # NOTE: this does ONE step of Q/REM processing.  it does NOT do
+        # MULTIPLE stages of Q/REM processing.  it *MUST* be PURE
+        # combinatorial and one step ONLY.
 
         # store intermediate tests (and zero-extended mantissas)
         am0 = Signal(len(self.i.a.m)+1, reset_less=True)
@@ -60,6 +65,6 @@ class FPDivStage1Mod(Elaboratable):
 
         m.d.comb += self.o.oz.eq(self.i.oz)
         m.d.comb += self.o.out_do_z.eq(self.i.out_do_z)
-        m.d.comb += self.o.mid.eq(self.i.mid)
+        m.d.comb += self.o.ctx.eq(self.i.ctx)
         return m