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[ieee754fpu.git] / src / ieee754 / fpdiv / div2.py

diff --git a/src/ieee754/fpdiv/div2.py b/src/ieee754/fpdiv/div2.py
index 7acb01b45e54bfb17bc5a8c56d49eb31b6e51ae7..43153fc93b842181b504ab7113fff4e2caf865c8 100644 (file)
--- a/src/ieee754/fpdiv/div2.py
+++ b/src/ieee754/fpdiv/div2.py
@@ -8,24 +8,27 @@ from nmigen.cli import main, verilog
 
 from ieee754.fpcommon.fpbase import FPState
 from ieee754.fpcommon.postcalc import FPAddStage1Data
-from .div0 import FPDivStage0Data
+from .div0 import FPDivStage0Data # XXX TODO: replace
 
 
-class FPDivStage1Mod(FPState, Elaboratable):
+class FPDivStage2Mod(FPState, Elaboratable):
     """ Second stage of div: preparation for normalisation.
     """
 
-    def __init__(self, width, id_wid):
+    def __init__(self, width, pspec):
         self.width = width
-        self.id_wid = id_wid
+        self.pspec = pspec
         self.i = self.ispec()
         self.o = self.ospec()
 
     def ispec(self):
-        return FPDivStage0Data(self.width, self.id_wid)
+        # TODO: DivPipeCoreInterstageData
+        return FPDivStage0Data(self.width, self.pspec) # Q/Rem in...
 
     def ospec(self):
-        return FPAddStage1Data(self.width, self.id_wid)
+        # XXX REQUIRED.  MUST NOT BE CHANGED.  this is the format
+        # required for ongoing processing (normalisation, correction etc.)
+        return FPAddStage1Data(self.width, self.pspec) # out to post-process
 
     def process(self, i):
         return self.o
@@ -50,6 +53,9 @@ class FPDivStage1Mod(FPState, Elaboratable):
         # last-stage guard/round/sticky and copies mantissa into z.
         # post-processing stages take care of things from that point.
 
+        # NOTE: this phase does NOT do ACTUAL DIV processing, it ONLY
+        # does "conversion" *out* of the Q/REM last stage
+
         with m.If(~self.i.out_do_z):
             mw = self.o.z.m_width
             m.d.comb += [
@@ -62,16 +68,16 @@ class FPDivStage1Mod(FPState, Elaboratable):
 
         m.d.comb += self.o.out_do_z.eq(self.i.out_do_z)
         m.d.comb += self.o.oz.eq(self.i.oz)
-        m.d.comb += self.o.mid.eq(self.i.mid)
+        m.d.comb += self.o.ctx.eq(self.i.ctx)
 
         return m
 
 
-class FPDivStage1(FPState):
+class FPDivStage2(FPState):
 
-    def __init__(self, width, id_wid):
+    def __init__(self, width, pspec):
         FPState.__init__(self, "divider_1")
-        self.mod = FPDivStage1Mod(width)
+        self.mod = FPDivStage2Mod(width)
         self.out_z = FPNumBaseRecord(width, False)
         self.out_of = Overflow()
         self.norm_stb = Signal()